Showing papers on "p–n junction published in 1977"

A method for determining the emitter and base lifetimes in p-n junction diodes

Abstract: A method is described that provides an experimental means for the first time to separate and determine the emitter and base lifetimes in a p-n diode after the junction has been fabricated. In the method, several static and transient measurements are analyzed using physical models of the diode characteristics. To illustrate the method, diffused silicon diodes are fabricated having substrate (base) impurity concentrations ranging from 1014to nearly 1017phosphorous atoms per cubic centimeter. The results show an emitter lifetime that is much smaller than the base lifetime in the diode having the highest base doping concentration. In this diode, the recombination current from the emitter is 65 percent of the recombination current from the base, demonstrating the significance of the emitter in governing the static current-voltage dependence. The importance of emitter recombination to the transient characteristics is also demonstrated. The paper emphasizes the techniques by which the base and emitter lifetimes are distinguished. It also demonstrates the need for carefully basing the quantitative analysis of the measurements on the underlying diode physics. The method described here applies not only to p-n diodes but also to junction solar cells and transistors.

A methodology for experimentally based determination of gap shrinkage and effective lifetimes in the emitter and base of p-n junction solar cells and other p-n junction devices

Abstract: An experimentally based methodology is described that determines the effective gap shrinkage and lifetime in the emitter of a p-n junction solar cell. It provides the first experimental means available for assessing the importance of gap shrinkage relative to that of large recombination rates in the highly doped emitter. As an additional result of the procedures employed, the base lifetime is also determined. The methodology pertains to a solar cell after the junction is formed. Hence each material parameter determined includes the effects of the processing used in junction fabrication. The methodology consists of strategy and procedures for designing experiments and interpreting data consistently with the physical mechanisms governing device behavior. This careful linking to the device physics uncovers the material parameters concealed in the data. To illustrate the procedures, they are applied to an n+-p solar cell having substrate resistivity of about 0.1 Ω cm.

Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance

Abstract: This disclosure relates to a method of making a V-MOS field effect transistor which does not require the extra steps of epitaxial growth in order to form the source area of the transistor. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor and is provided with enhanced source capacitance.

Method of semiconductor solar energy device fabrication

Abstract: This disclosure relates to a semiconductor solar energy device which is of the PN-type and utilizes a dielectric anti-reflective coating on the side of the device that faces the sunlight. The fabrication techniques used in making this semiconductor device include the use of a rough or textured pyramid shaped silicon surface beneath the anti-reflective coating to increase solar cell efficiency. Also, ion implantation is used to form the PN junction in the device. The ion implanted region located on the side of the device that is subjected to the sunlight is configured in order to permit metal ohmic contact to be made thereto without shorting through the doped region during sintering of the metal contacts to the semiconductor substrate. The dielectric anti-reflective coating, in one embodiment, is a composite of silicon dioxide and silicon nitride layers. The device is designed to permit solder contacts to be made to the P and N regions thereof without possibility of shorting to semiconductor regions of opposite type conductivity.

Confined‐carrier luminescence of a thin In1−xGaxP1−zAsz well (x∼0.13, z∼0.29, ∼400 Å) in an InP p‐n junction

Abstract: A thin (∼400 A) LPE In1−xGaxP1−zAsz ’’trap’’ on the p‐type side of an InP junction [Eg(InP)−Eg(InGaPAs) ≡ΔE∼245 meV], is filled by injection to a high enough density to make it possible to observe confined‐particle states and laser modes in a 70‐meV (≳600 A) range. The position of the modes is in good agreement with the transition energies expected for a finite potential well.

A novel double‐heterostructure p‐n‐junction laser

Abstract: Oxide‐stripe laser and Burrus LED technologies have been combined to enable DH GaAlAs p‐n‐junction lasers with emission perpendicular to the junction plane to be prepared.

The dependence of open-circuit voltage on illumination level in p-n junction solar cells

Abstract: Simple analytical dependencies of solar cell open-circuit voltage on illumination level, valid for high injection, are derived. The developments are guided and verified by exact computer-aided numerical simulations of silicon cells. The results are related to an easily measured device parameter, the uncompensated photocurrent, through the use of the principle of superposition. An advantage of p+-n over n+-p cells with respect to open-circuit voltage at high levels of illumination is predicted.

Method of making semiconductor device with PN junction in stacking-fault free zone

Abstract: In a method of making a semiconductor device, a semiconductor wafer having a stacking fault originally contained in the wafer or produced in the wafer through the thermal oxidation of the wafer surface is subjected to an annealing treatment in a non-oxidative atmosphere to eliminate the stacking fault. A PN junction is thereafter formed in an area of the wafer from which the stacking fault is eliminated.

Shape of the p‐n junction and crystalline structure of CuxS‐CdS thin‐film solar cells

Abstract: CuxS‐CdS solar cells, prepared by the Clevite process, were bevelled at an angle of 40′ and suitably etched to expose grains of CdS, cracks, and the junction region. SEM pictures of this region reveal the average grain size and the distance between the cracks to be about 0.5 and 2 μm, respectively. Cathodoluminescence and SEM studies of the bevelled region of the cells show that the thickness of the CuxS layer perpendicular to the surface is highly nonuniform and thus forms vertical junctions. With the help of simple expressions it was shown that the reduction of the open‐circuit voltage is a natural outcome, if the vertical parts of the junction are considered. It was also pointed out that there may be an optimum grain size of the CdS crystallites to obtain maximum power output from the cell.

AC silicon PN junction photodiode light-valve substrate

Abstract: There is disclosed a single crystal silicon charge storage apparatus suitable for use in an alternating current driven liquid crystal light valve having therein a PIN photodiode structure. The charge storage medium is made of a high resistivity substrate on which an MOS capacitor is formed having fast photoelectric transient response an capable of operating over a wide frequency range. A PIN photodiode structure is provided on one side of the substrate next to the MOS capacitor to deplete the substrate of its mobile charge carriers during a portion of the AC cycle and to collect the electric field-guided signal representing charge carriers that are generated or introduced into the substrate by an input mechanism. The signal from the substrate is electrically coupled through high-reflectivity mirrors and light blocking layers to the liquid crystal.

Method and apparatus for measuring minority carrier lifetimes and bulk diffusion length in P-N junction solar cells

Abstract: Carrier lifetimes and bulk diffusion length are qualitatively measured as a means for qualification of a P-N junction photovoltaic solar cell by alternately applying high frequency (blue) monochromatic light pulses and low-frequency (red) monochromatic light pulses to the cell while it is irradiated by light from a solar simulator, and synchronously displaying the derivative of the output voltage of the cell on an oscilloscope. This output voltage is a measure of the lifetimes of the minority carriers (holes) in the diffused N layer and majority carriers (electrons) in the bulk P material, and of the diffusion length of the bulk silicon. By connecting a reference cell in this manner with a test cell to be tested in reverse parallel, the display of a test cell that matches the reference cell will be a substantially zero output.

Semiconductor controlled luminescent device

Abstract: A p type semiconductor gate layer is buried in an N type semiconductor cathode layer to encircle a channel through which the forward current of a luminescent PN junction passes. A reverse voltage is applied to the gate layer to spread a depletion layer in the channel to control the forward current and therefore the emission of light. The gate layer may be disposed on that surface of the cathode layer remote from the luminescent PN junction with a groove disposed the other surface of the cathode layer to narrow the channel.

High bandgap window layer for GaAs solar cells and fabrication process therefor

Abstract: The specification describes a semiconductor solar cell and fabrication process therefor wherein a thin N-type gallium arsenide layer is deposited on a larger P-type substrate layer which is selected from the group of III-V ternary compounds consisting of aluminum phosphide antimonide, AlPSb, and aluminum indium phosphide, AlInP. P-type impurities are diffused from the substrate layer into a portion of the thin N-type gallium arsenide layer to form P-type region therein which defines a PN junction in the thin gallium arsenide layer. Thus, the quantity of gallium arsenide required to provide this PN photovoltaic junction layer in the cell is minimized, and the P-type substrate serves as a high bandgap window layer for the cell. Such high bandgap of this window material is especially well suited for efficiently transmitting the blue spectrum of sunlight to the PN junction, thus enhancing the power conversion efficiency of the solar cell.

Bipolar integrated semiconductor structure including I2 L and linear type devices and fabrication methods therefor

Abstract: This disclosure relates to a bipolar integrated semiconductor structure that has incorporated therein both I2 L and linear type bipolar devices. The integrated structure utilizes a double epitaxial layer deposited or formed on a starting substrate wherein at least one linear type bipolar device is incorporated in one portion of the final integrated structure and at least one I2 L bipolar device is incorporated in another portion of the final double epitaxial layer integrated structure. For the linear type bipolar device, the subcollector region is selectively located between the starting substrate and the first epitaxial layer whereas for the I2 L bipolar device, the sub-emitter region is selectively located between the first and the second epitaxial layers. Other features of the bipolar integrated semiconductor structure include polysilicon isolation for the I2 L and linear devices, up and down diffused PN junction isolation type regions, up-diffused base region for the I2 L device, Schottky type collectors for the I2 L device, up and down diffused base regions for the I2 L device isolate the collector contacts, and the use of another subcollector region selectively located between the first and the second epitaxial layer in the linear portion of the integrated semiconductor structure which functions to improve the current gain of the lateral PNP linear transistor device.

High frequency ion implanted passivated semiconductor devices and mircowave intergrated circuits and planar processes for fabricating both

Abstract: The specification describes new high frequency ion implanted semiconductor devices, novel microwave integrated circuits employing same, and a planar fabrication process for both wherein initially an ion implantation and PN junction passivation mask is formed on one surface of a semiconductor substrate. Next a heavily doped buried region is ion implanted through an opening in the mask and into the substrate to a preselected controlled depth. Thereafter, one or more additional ion implants are made through the mask opening to complete the active device regions and a PN junction therebetween, all of which are bounded by an annular, higher resistivity unimplanted region of the semiconductor substrate. The PN junction thus formed terminates beneath the implantation and passivation mask, and the semiconductor substrate is then annealed to remove ion implantation damage and to electrically activate the ion implanted regions, while simultaneously controlling the lateral movement of the PN junction beneath the passivation mask. Such annealing does not adversely affect the conductivity and passivation characteristics of either the higher resistivity region or the passivation mask. Openings to the heavily doped buried regions in the substrate are made both opposite and coaxial to the openings in the passivation mask. Precision in the area and depth of these contact openings is achieved by use of a chemical etchant that is preferential to the substrate crystallographic orientation and the impurity concentration levels. Ohmic contact metallization is deposited into the contact openings after which the heat sink metallization is applied to either or both of the metallized contact regions.

Improved theory of the silicon p-n junction solar cell

Abstract: The theory of the silicon p-n junction solar cell in its present state is inadequate to explain the observed fall-off in power output and open-circuit voltage with increasing substrate doping. The present work removes this deficiency by incorporating into the theory the generation-recombination dark current in the junction appropriately corrected for the thermal counterpart of the Franz-Keldysh effect. The light generated short-circuit current is calculated from the known solar spectrum and band gap and from estimates of reflection, absorption, obstruction, transmission, and recombination losses. The improved theory permits a detailed quantitative explanation of the experimentally measured current-voltage characteristics of conventional, violet, and nonreflective silicon solar cells for beginning-of-life and end-of-life performance in a space environment and as a function of thickness. It also explains the temperature coefficient of the short-circuit current, of the open-circuit voltage, and of the power output of these three types of cell. Finally, the theory explains the observed fall-off in power output and open-circuit voltage with increasing substrate doping and predicts the maximum efficiency to be expected in state-of-the-art material for optimized cell thickness and doping for both beginning-of-life and end-of-life situations. 34 references.

Method of low dose phoshorus implantation for oxide passivated diodes in P-type silicon

Abstract: Low dosage phosphorus implantation regions in P-type silicon are subjected to a severe damage implant with halogen or silicon ions, preferably fluorine and chlorine. This permits anneal in a strongly oxidizing atmosphere for PN junction passivation, without concurrently inducing PN junction leakage. Oxide passivated PN junctions are formed having leakages as low as when the low dose phosphorus implants are annealed in other atmospheres, or are formed in silicon.

Method of producing a PN junction type solar battery

Abstract: A PN junction type solar battery comprising a plurality of alternate P-type and N-type semiconductor layers provided in a laminated manner parallel to an incident-light-receiving plane, connection ears provided opposite to each other and integrally connected to one end of each of the P-type and N-type semiconductor layers respectively, the connection ears being made of material of the same conduction type as the semiconductor layers respectively, and terminal electrodes mounted on the connection ears of the P-type and N-type semiconductor layers respectively so as to obtain ohmic contact therebetween. A method of producing a PN junction type solar battery in which P-type and N-type semiconductor layers are formed on a substrate in a staggered manner relative to each other preferably by the ion-beam deposition method or the cluster-ion-beam deposition method.

Rectification effects based on the p‐n junction of poly[γ‐ (β‐N‐carbazolylethyl) ‐L‐glutamate]— 2,4,7‐trinitrofluorenone systems

Abstract: In the dark and under illumination, it has been found that rectification effects in an organic photoconductor system are attributable to a p‐n junction barrier. This junction was accomplished by a doping process similar to one used in inorganic semiconductors. The p‐n junction barrier was made by immersing a poly[γ‐ (β‐N‐carbazolylethyl) ‐L‐glutamate] (PCLG) film in either benzene or a methylethylketone solution of 2,4,7‐trinitrofluorenone (TNF), since both benzene and methylethylketone are poor solvents for PCLG and are suitable solvents for TNF. PCLG and PCLG doped with TNF behave as p‐type and n‐type organic semiconductors, respectively, and a p‐n junction with a continuous interface can be accomplished in the sandwich structure system of In2O3//PCLG/PCLG‐TNF complex//Au. In this sample, rectification effects both in the dark and under illumination have been observed to be in good agreement with a theoretical equation of the p‐n junction for inorganic semiconductors. However, the potential drop across ...

Mesa type semiconductor device

Abstract: A P type semiconductor layer is epitaxially grown on an N + type semiconductor substrate to form a PN junction between them so as to expose its circumference to the peripheral surface of the substrate. The P type layer is formed into a mesa having a tilted surface to which the circumference of the PN junction is exposed. Then an N + type diffusion layer is disposed on the tilted mesa surface to protect the PN junction.

Temperature-compensated voltage reference diode with intermediate polycrystalline layer

Abstract: Disclosed is a temperature-compensated voltage reference diode comprising a breakdown PN junction for establishing the zener breakdown voltage, a PN junction for temperature compensation having a temperature coefficient opposite to that of the breakdown PN junction, the breakdown PN junction and the temperature-compensating PN junction being integrally formed in a semiconductor substrate in a laminated fashion with these PN junctions connected in inverse series with each other, and a semiconductor region interposed between the breakdown PN junction and the temperature compensating PN junction for substantially preventing a transistor action from taking place between the respective PN junctions, wherein the semiconductor region is formed of at least one of a polycrystalline semiconductor layer and a single crystal semiconductor layer having an impurity concentration of higher than about 5×10 18 atoms/cm 3 .

A substrate etch geometry for near ideal breakdown voltage in p-n junction devices

Abstract: A new junction-termination geometry is proposed which can be achieved by a simple etch. This etch effectively lowers peak surface fields in both plane and planar p-n junction devices without increasing peak bulk electric fields. This insures an ideal, or near-ideal, avalanche breakdown voltage. The further advantages of the proposed technique lie in a relative insensitivity to etch depth, a minimal loss in device area, and compatibility with planar technology. Theoretical and experimental results are given to illustrate the substrate-etch technique.

Cadmium diffused Pb{hd 1{31 x{b Sn{hd x{b Te diode laser

Abstract: A higher power infrared Pb1-xSnxTe diode laser that is tunable at this high output power at all wavelengths from 65 - 32 microns, particularly 65 - 9 microns The diode laser has a P-type laser cavity with a degenerate carrier concentration A low carrier concentration N-type region is adjacent the P-type region The N-type region has unique characteristics inherent to a cadmium diffusion from an external source at a temperature of about 350 DEG - 500 DEG C The cadmium diffusion N-type region forms a flat PN junction with the P-type laser cavity Dislocation density in the monocrystal forming the completed laser body, even after the cadmium diffusion, is not noticeably higher than in the monocrystal from which the laser is made A method of forming such a laser, using a short time, low temperature cadmium diffusion process, is claimed

Green light emitting diode

Abstract: A green light emitting diode of gallium phosphide having an epitaxial layer consisting of P and N type layer portions. A donor concentration in the N type layer, an acceptor concentration gradient in the P type layer and nitrogen concentration near the pn junction are selected respectively at predetermined values.

Method of manufacturing semiconductor devices having isoelectronically built-in nitrogen and having the p-n junction formed subsequent to the deposition process

Abstract: A method of manufacturing by liquid epitaxy III-V semiconductor crystals comprising a layer having isoelectronic nitrogen trapping centers. The method is characterized in that the deposition of the nitrogen-doped layer is succeeded by the deposition of a deep layer containing less nitrogen doping after which a p-n junction is formed in the first layer.

The non-linearity of the temperature response of silicon p-n junction radiation detectors operated in the DC mode

Abstract: The non-linearity of the radiation current response to temperature was examined in detail, and the theoretical interpretation of the experimental results was extended to include the carrier trapping and detrapping effects, which are not incorporated in the direct current equation derived by Scharf (1967).

Method of making a single chip temperature compensated reference diode

Abstract: A reference diode and a method for making same are described, wherein a single wafer of semiconductive material is processed to provide a reverse PN junction acting in its breakdown region and to provide one or more forward PN junctions in electrical series with the reverse junction. A wafer of semiconductive material of one conductivity type is diffused with an impurity to form a plurality of regions of semiconductive material of opposite conductivity type. The regions are laterally displaced from each other and each forms a reverse PN junction at the interface between the region and the remainder of the wafer. An impurity is then diffused into one or more of these regions to form one or more forward PN junctions. An additional reverse PN junction is then formed between and adjacent to two of the previously formed regions. The latter reverse PN junction is formed by alloying or diffusing an impurity into the wafer to provide a region of opposite conductivity type having a higher conductivity than the adjacent regions. The reverse PN junction thus formed by the latter step exhibits a lower breakdown voltage than the adjacent reverse PN junctions. All exposed PN junctions extend to only one surface of the wafer and are passivated. Metal contact pads are then deposited on the opposing faces of the wafer to permit axial connections to the temperature compensated diode.

Thyristor fired by overvoltage

Abstract: A thyristor having an auxiliary cathode emitter region disposed in the central portion of the device in PN junction relationship with a cathode base region is disclosed. An extra impurity region of the same conductivity type as the cathode base region is disposed in the cathode base region in the central portion of the device inwardly of the outer boundary of the auxiliary cathode emitter. The extra impurity region has a higher impurity density gradient adjacent the common PN junction formed by the cathode and anode base regions than the remainder of such junction.