Showing papers on "Parasitic capacitance published in 1985"

VLSI wiring capacitance

Abstract: Accurate prediction of device current and the capacitance to be driven by that current is key to the design of integrated logic and memory circuits. A finite-element algorithm is described which simulates the capacitance of structures with general shape in two or three dimensions. Efficient solution of the linear equations is provided by the incomplete Cholesky conjugate gradient method. The model is used to simulate the wiring capacitance of a 1.25-micrometer VLSI technology. The predicted capacitances of closely spaced first-metal polycide-gate and second-metal conductors used in this technology agree with measured results. The simulated three-dimensional capacitance of a second-metal line crossing a first-metal line is twice that found when estimated by two-dimensional models. The effect of line-to-line capacitance on the noise margin of logic circuits and on the signal in a dynamic RAM is examined. This capacitance presents a limit to wiring density for logic circuits and is a significant signal detractor in dynamic RAMs with closely spaced metal or diffused bit lines.

Self-calibration method for capacitors in a monolithic integrated circuit

Abstract: A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted. In another aspect of the invention, capacitance-adjustment steps are sequentially interleaved with analog-to-digital conversions in an analog-to-digital converter.

Ultra-low-capacitance flip-chip-bonded GaInAs PIN photodetector for long-wavelength high-data-rate fibre-optic systems

Abstract: A novel GaInAs substrate illuminated photodetector structure is reported for the 1.0–1.7 μm wavelength range with capacitance as low as 0.02 pF, packaging stray capacitance below 0.02 pF, 97% quantum efficiency and subnanoampere leakage current. The device is rugged, epoxy-free, does not use an integral fibre pig-tail and wire bonding to the detector chip is not required.

Magic's Circuit Extractor

Abstract: We have implemented a fast hierarchical circuit extractor for the Magic VLSI layout system. The keys to its speed are a new algorithm based on corner-stitching, and its ability to extract cells incrementally. Because the extractor is incremental, typically only a few cells must be re-extracted when the layout changes. The extractor computes circuit connectivity and transistor dimensions, both internodal and substrate parasitic capacitance, and parasitic resistances. It is parameterized to work across a wide range of MOS technologies.

Power source for electric discharge machining

Abstract: A power source for electric discharge machining, which performs a semi-mirror-finish machining operation with a surface roughness of 1 μm Rmax or less. The power source includes either a resonance circuit or an impedance matching circuit so that the electric discharge is carried out under the condition that resonance is caused to occur with the capacitance of an interelectrode gap between an electrode and a workpiece to be machined or the impedance-matching is effected in response to variation in interelectrode condition. With such a power source, it is possible to eliminate the effect of the stray capacitance exsiting in a current supplying line and also to eliminate the shortcoming due to variation on the interelectrode condition, and therefore a mirror-finished machining operation can be stably carried out to provide machined surfaces excellent in surface roughness.

Capacitive pressure sensor with low parasitic capacitance

Abstract: A plurality of two-plate capacitive pressure sensors with low parasitic capacitance and easily accessible plates are made with microcircuit and thin film technology by depositing a thin layer of glass over a plurality of thin, rigid plates and thin, narrow electrodes previously deposited on a thick glass dielectric substrate, by etching cavities in the thin layer of glass over the plates, and by anodically bonding, in vacuum, thin, doped silicon diaphragms to the thin layer of glass to form variable capacitors each of whose capacitance varies with the pressure outside the sensor.

High-frequency modulation of 1.52 μm vapour-phase-transported InGaAsP lasers

Abstract: We describe modifications to the recently demonstrated vapour-phase-transported laser structure to reduce the parasitic capacitance by an order of magnitude, and increase the 3 dB bandwidth for CW 1.52 μm lasers to 8 GHz. The parasitic and nonlinear limitations to this bandwidth are discussed.

High Gain Equalizing Amplifier Integrated Circuits for a Gigabit Optical Repeater

Abstract: Equalizing amplifier circuits for a gigabit optical-fiber transmission system are integrated on two monolithic chips implementing an advanced silicon bipolar process. Several new circuit techniques such as a broad-band 50-/spl Omega/ matching amplifier and an electrically controlled and adjusted peaking technique are employed. It is clarified that the main degradation factors of circuit stability are parasitic capacitance between the input and output terminals, and the crosstalk occuring through the wire bonding inductance. The maximum gain and 3-dB down bandwidth of the equalizing amplifier IC's are 64 dB and 1.2 GHz, respectively. The noise figure obtained is 4.5 dB within the dc to 2-GHz range.

Switched capacitor precision difference amplifier

Abstract: A circuit which can selectively sample and hold two real time input voltages and provide an output voltage indicating the difference value of the input voltages is provided. A switched capacitor structure which provides no parasitic capacitance output error component when the two input voltages are substantially equal is used.

Ring topology for an integrated circuit logic cell

Abstract: An improved topology for a multi-input Boolean logic circuit whereby the circuit can be realized in integrated circuit form while consuming less area on the semiconductor wafer and exhibiting lower parasitic capacitance than equivalent integrated circuits using conventional topology. Rather than employing what might be described as an "in-line" topology of the prior art, a ring topology is used wherein adjacent MESFET's share a common region for source, drain, or source/drain contacts and wherein the amount of second level interconnect required is minimized.

Circuit for generating a substrate bias

Abstract: A substrate bias generator in which the junction point of the capacitance and the diode of the charge pump is connected to the earth point of the circuit (and of the further circuit on the substrate for which the bias is generated) via two or more series-connected transistors. During the charging period of the capacitance the transistors are (fully) conductive, hence the capacitance is optimally charged as the conductive transistors cause no (or hardly any) voltage drop. During the pumping cycle all transistors are diode-connected, bringing about a negative voltage with respect to the earth point at the junction point, which negative voltage is limited by the sum of the threshold voltages of the diode - connected transistors.

A 30 GHz Monolithic Single Balanced Mixer with Integrated Dipole Receiving Element

Abstract: This paper will describe a 30-GHz monolithic low-noise balanced mixer which has been developed using an integrated bow-tie antenna to waveguide transition and low parasitic Mott diodes. The diodes and mixer circuit were developed using MBE material and were fabricated using a plated airbridge technology. Measurements on the diode at dc and RF showed that the zero bias junction capacitance was 0.025 pF and the series resistance was 10 Omega. A mixer conversion loss of 6 dB was measured at 30 GHz with an IF of 1 GHz.

A scaleable technique for the measurement of intrinsic MOS capacitance with atto-Farad resolution

Abstract: An on-chip capacitance measurement technique used for interline capacitances has been extended to MOS transistor capacitance measurements. The gate of the test transistor is connected to a reference capacitance made on the same chip. Small ac signals are applied to one of the transistor terminals successively. The magnitude of the ac voltages appearing on the gate node is measured indirectly. C_{gd}, C_{gs} , and C gb are calculated accurately from the measured ac voltage and the reference capacitance value. It was found that C gd and C gs are measured completely free of parasitic capacitances resulting from both the internal on-chip circuit and external wiring. The on-chip circuitry is simple and can easily be scaled down. These features insure this technique is the most suitable for the measurement of minimum, geometry transistors with atto-Farad-range resolution. It is shown that this technique has the ability to detect the capacitance difference which comes from the misalignment of source and drain metal connections. Measurements with this technique are used to first describe the short- and narrow-channel effects on MOS transistor capacitance.

Vertical channel field effect transistor

Abstract: A semiconductor device component, and process for preparation thereof, wherein current flowing in a vertical channel of semiconductor material is controlled by metallic gates laterally disposed on either side of the channel. Insulator layers are positioned overlying and underlying each gate, to reduce parasitic capacitance which would otherwise be present if the metallic gate material were in contact with overlying and underlying semiconductor material. Reduction of the capacitance allows the use of wider gate strips, thereby reducing the series resistance to an external gate contact. These changes significantly improve the high-power, high-frequency performance of the device component, as compared with permeable base transistors.

RF field generator and detector

Abstract: An RF field generator and detector comprising an RF coil having an inductance and at least one conductor which includes at least first and second separated parts arranged to form stray capacitance between them, capacitors for impedance matching which are connected to the RF coil, and a balanced-to-unbalanced transformer by which a balanced load composed of the RF coil and the capacitors is coupled to an unbalanced RF transmitter and receiver, the stray capacitance being adjusted thereby to equivalently reduce the inductance of the RF coil.

Two transistor DRAM cell and array

Abstract: A two transistor Dynamic Random Access Memory Cell and Array Use of two pass transistors in series for the cell provides numerous additional capabilities for the DRAM array, and, in the preferred embodiment, provides bitline segment multiplexing, so that the sense amplifier pitch can be increased while the bitline capacitance as seen by the sense amplifier and by the memory cell is reduced To accomplish this, the parasitic capacitance of the node between the two series pass transistors is kept to a minimum

Static and transient latch-up hardness in N-well CMOS with on-chip substrate bias generator

Abstract: Theoretical considerations and experimental results of the influence of an on-chip substrate bias generator on static and transient latch-up hardness in n-well CMOS are presented. The current drive capability of the V BB generator is limited, its internal resistance is operating point dependent. If the V BB generator is not capable to sink the static and the time averaged transient substrate currents, localized forward biasing of the substrate takes place, thus triggering latch-up. A special clamp circuit was used for limiting the forward substrate bias below the value capable to trigger the parasitic SCR. Using such clamping techniques the latch-up hardness with on-chip bias generator can significantly be improved during power-up and in normal operation mode.

Capacitance measuring method and apparatus

Abstract: An apparatus for performing ratiometric capacitance measurements by comparing the output of a digital-to-analog converter with the voltage at a tap between an unknown capacitance and a first inherent capacitance of the apparatus. A common input voltage is supplied to both the series circuit, including the first inherent and unknown capacitances, and to the digital-to-analog converter which accomplishes attenuation of the input voltage in response to a digital value. The digital value is generated by a successive approximation register supplying a digital output relating the unknown capacitance to the known capacitance. The apparatus is adapted to ratiometrically measure the first inherent capacitance by supplying the common input voltage to a series circuit, including a known reference capacitance and the first inherent capacitance, such that the digital output of the successive approximation register relates the first inherent capacitance to the reference capacitance. The apparatus is further adapted to ratiometrically measure a second inherent capacitance by supplying the common input voltage to a series circuit, including the first and second inherent capacitances, such that the digital output of the successive approximation register relates the second inherent capacitance to the first inherent capacitance. The measured value of the unknown capacitance is then corrected by the amount of the second inherent capacitance appearing in parallel with the unknown capacitance during measurement thereof with reference to the first inherent capacitance.

Differential pair with compensation for effects of parasitic capacitance

Abstract: First and second transistors are connected as a differential pair, and a third, current source transistor has its collector connected to the emitters of the first and second transistors and draws a first constant current. Fourth and fifth transistors are connected as a second differential pair with the collectors of the fourth and fifth transistors connected to the collectors of the first and second transistors respectively and with the bases of the fourth and fifth transistors connected to the bases of the second and first transistors respectively. A sixth, current source transistor has its collector connected to the emitters of the fourth and fifth transistors and draws a second constant current that is much smaller than the first constant current. All four transistors of the two differential pairs are essentially identical, and the two current source transistors have the same parasitic capacitances. Consequently, the displacement currents associated with the parasitic capacitance at the collector of the third transistor is replicated at the sixth transistor, and the contributions of the two displacement currents to the collector currents of the differential pairs are common mode, and are substantially cancelled. Feedthrough at the base/collector junctions of the first and second transistors is at least partially cancelled by feedthrough at the base/ collector junctions of the fourth and fifth transistors respectively.

The Stray-Capacitance Equivalent Circuit for Resistive Voltage Dividers

Abstract: An equivalent circuit for the stray capacitances of resistive voltage dividers is proposed. The parameters of the equivalent circuit are determined from the electrostatic field of the divider. The stray-capacitance equivalent circuit for a 12.75-k? divider has been determined and its step-response has been computed. The computed stepresponse agrees well with the measured step-response.

A Scaleable Technique for the Measurement of Intrinsic MOS Capacitance with Atto-Farad Resolution

Abstract: An on-chip capacitance measurement technique used for interline capacitances has been extended to MOS transistor capacitance measurements. The gate of the test transistor is connected to a reference capacitance made on the same chip. Small ac signals are applied to one of the transistor terminals successively. The magnitude of the ac voltages appearing on the gate node is measured indirectly. C/sub gd/,C/sub gs/ and C/sub gb/ are calculated accurately from the measured ac voltage and the reference capacitance value. It was found that C/sub gd/ and C/sub gs/, are measured completely free of parasitic capacitances resulting from both the internal on-chip circuit and external wiring. The on-chip circuit is simple and can easily be scaled down. These features insure this technique is the most suitable for the measurement of minimum-geometry transistors with atto-Farad-range resolution. It is shown that this technique has the ability to detect the capacitance difference which comes from the misalignment of source and drain metal connections. Measurements with this technique are used to first describe the short- and narrow-channel effects on MOS transistor capacitance.

Output voltage waveform improvement of the coaxial Marx‐type high‐voltage generator

Abstract: A metal ring was installed to each of the main capacitor modules of the coaxial Marx‐type high‐voltage generator to increase the stray capacitance between the main capacitors and the cylinder of the outer conductor. Improvements in build‐up time of the output voltage were achieved and good agreements were obtained between the experimental and the simulated results.

Surface-oriented low-parasitic Mott diode for EHF mixer applications

Abstract: The design and fabrication of a novel air-bridged, low-parasitic Mott diode is described. The devices were fabricated on epitaxial layers grown by MBE on SI undoped LEC substrates. Measurements on the diode at DC and RF showed that the zero bias capacitance was 0.025 pF, the parasitic capacitance 0.007 pF and the series resistance was approximately 10 ?. Diode pairs were incorporated into monolithic single balanced mixers which exhibited a conversion loss of 6 dB at 30 GHz with a 1 GHz IF.

Protection device for a transmitter output

Abstract: The device to be inserted between the transmitter (5) and its antenna (A) comprises, in series in the line which connects the antenna (A) to the transmitter (5), a spark gap (1), a first transformer ( 3), two protection diodes (D1, D2) and a second transformer (4). The role of the two transformers is to achieve a drop in line impedance at the place where the diodes (D1, D2) are inserted in order to prevent the parasitic capacitance of these diodes from disturbing the device. Application to the protection of transmitters mainly between 3 and 300 MHz.

Information input/output display device

Abstract: An information input output display device comprising a dielectric (6,20) which is held in a portion between one electrode (18) and an other electrode (19) opposite to each other and which has at least a first state and a second state of unequal capacitances, means (7,8;25,26) to change the capacitance of the dielectric, capacitance holding means (11) to hold at least temporarily a value of the capacitance of the dielectric in the first state, and means (12) to compare the value of the capacitance of the dielectric with the value of the capacitance held by the capacitance holding means (11), whereby information can be read out without being affected by fluctuations in a distance d between the electrodes oriand in an ambient temperature T.

Pulse width generating circuit synchronized with clock signal and corresponding to a reference voltage

Abstract: A pulse generating circuit is provided for generating a pulse having a time width synchronized with an input pulse and corresponding to a reference voltage. The circuit is particularly designed not to be affected by parasitic capacitance. A circuit for charging one electrode of an integrating circuit with a constant current is controlled by turning on or off a switch in response to the input pulse. The other electrode of the integrating capacitor is connected with a reference voltage source by driving a switch in response to a pulse having a pulse width which contains the time period of the input pulse and which is wider than the input pulse. A comparator is provided for comparing the potential at one electrode of the integrating capacitor and ground potential. A desired pulse is generated by a logic circuit which is receives both the output of the comparator and the input pulse.

Quasi-two-dimensional simulation of transient latchup effect in VLSI CMOS circuits

Abstract: The transient latchup behavior of a typical n-well CMOS structure has been simulated using the program MEDUSA. A quasi-2D representation of the parasitic thyristor was developed by describing the vertical and lateral bipolar transistor paths with 1D numerical models. The dependence of latchup behavior on circuit layout and external stimuli as well as on doping profiles was investigated. Good agreement with experimental results was obtained showing that the two-dimensional nature of the latchup effect can sufficiently be taken into account by this approach and a realistic description of the circuit surrounding of the latchup path can be achieved. Computation costs, however, are much less compared to a rigorous 2D transient analysis. A simple RC network representation of the critical latchup path is derived which allows the estimation of the maximum achievable forward bias of the bipolar transistors caused by power-up transients.

Semiconductor ic device

Abstract: PURPOSE:To contrive to improve the operating speed by reduction of the parasitic capacitance between the diffused layer under a wiring and a substrate by a method wherein the diffused layer under the wiring serving as the wiring region is subdivided by means of a U-groove isolating region. CONSTITUTION:The diffused layer at the part serving as the wiring region, i.e., an N epitaxial layer 13 and an N buried layer 12 is finely split by the U- groove isolating region 5 so formed as to reach the semiconductor substrate 11. The parasitic capacitance CTS between the layer 12 and the substrate considerably reduces with the decrease in junction area. This leads to the same condition that the wiring capacitance CSO and the parasitic capacitance CTS are connected in series between the wiring L on the surface of an oxide film 14 and the substrate on which a power source voltage VCC such as 5V is impressed. Since the capacitances CSO and CTS are in the same order, the wiring capacitance is reduced to approx. a half in appearance.

Compensation circuit and method for stabilization of a circuit node by multiplication of displacement current

Abstract: A compensation circuit for stabilization of a circuit node (40) coupled to an integrated circuit substrate by a parasitic capacitance of a value C1 has a displacement current substantially equal to C1 dv/dt. A switching device (42) having a gain beta (beta) can either supply a current to, or draw a current from, the circuit node (40, 60) substantially equal to C2 beta dv/dt which is greater than the displacement current thereby obviating oscillation of an integrated circuit output due to capacitive coupling of the substrate to sensitive circuit nodes.