Showing papers on "Parasitic capacitance published in 1993"

A new and reliable direct parasitic extraction method for MESFETs and HEMTs

Abstract: A novel and accurate analytical direct extraction method for the determination of MESFET and HEMT parasitic elements is described. The technique differs from the commonly used "cold-FET" technique by avoiding the forward biasing of the Schottky gate junction. The parasitic capacitances, inductances and resistances are directly extracted from S-parameter measurements under pinched-FET and zero-bias conditions. Ambiguities commonly observed during resistance extraction using cold-FET techniques are avoided with the new method.

Methods for fabrication of thin film inductors, inductor networks and integration with other passive and active devices

Abstract: The fabrication of thin film inductors on a substrate, which may include thin film resistors, thin film capacitors, and semiconductor devices. In one embodiment an inductor is fabricated initially on a substrate and then integrated with other devices subsequently formed on the substrate. In this embodiment, process steps used to fabricate such other devices utilize temperatures sufficiently low to prevent damaging or destroying the characteristics of the inductor. In another embodiment the fabrication of an inductor is achieved through photoresist masking and plating techniques. In alternative embodiments, fabrication of an inductor is achieved by sputtering, photoresist processes and etching/ion-milling techniques. A combination of various individual process steps from various embodiments are suitable for use to fabricate the individual layers to achieve a structure of this invention. The inductor fabricated in accordance with this invention is connected to other passive or active components through metal interconnections in order to improve the frequency performance of the inductor. In certain embodiments, parasitic capacitance of the inductor is significantly reduced by fabricating inductor coils on dielectric bridges. In certain embodiments, a magnetic core of ferromagnetic material is used to improve the performance of the inductor at frequencies below about 100 MHz.

A newly designed planar stacked capacitor cell with high dielectric constant film for 256 Mbit DRAM

Abstract: Thin film of (Ba/sub 0.75/Sr/sub 0.25/)TiO/sub 3/ with equivalent SiO/sub 2/ thickness of 0.47 nm has been developed for capacitor dielectric film of 256 Mbit DRAM. A novel cell design named FOGOS (FOlded Global and Open Segment bit-line cell) structure is also proposed for 256 Mbit DRAM. By combining high dielectric constant film and FOGOS design, we have succeeded in making a practical and integrated cell that has sufficient cell capacitance with planar stacked capacitor, small bitline parasitic capacitance and large lithographic tolerance of alignment and DOF. 0.72 /spl mu/m/sup 2/ cell size based on 0.25 /spl mu/m process technology is realized. >

Double and triple charge pump for power IC: dynamic models which take parasitic effects into account

Abstract: An optimized design methodology for the double and triple charge pump is proposed. The circuits discussed given an output voltage greater than the supply voltage and are commonly used to power 1C or memory to allow the switching on of an MOS device. Theoretical models of charge pumps in the transient region are given. The models take parasitic capacitances and current leakage into account. They allow better knowledge of the circuit dynamics to be obtained and an optimized design to be achieved. >

Constant frequency, zero-voltage-switching converters with resonant switching bridge

Abstract: A novel, compact, converter structure utilizes a switching bridge configuration to provide a low voltage stress, constant frequency controlled converter whose switches and diodes all turn-on and turn-off with zero-voltage-switching. The novel converter configuration uses a full-bridge switching circuit comprising four diodes D1 -D4 and, in one embodiment, four active semiconductor switches S1 -S4. A resonant inductor Lr is connected across the bridge nodes a and b, and parasitic capacitance of the diodes and active switches S1 -S4 are incorporated in an L-C circuit. Connected in parallel with the bridge is a voltage source or sink, depending on the direction that power will flow; and connected to node a or b is a current source or sink, again depending upon the direction of power flow. The present invention stores sufficient energy in the resonant inductor Lr so that prior to each switch or diode commutation, charge present on the corresponding parasitic capacitance of that semiconductor may be removed by the current drawing action of the resonant inductor Lr. In this way, all diodes D1 -D4 and active switches S1 -S4 operate with zero-voltage-switching. The novel bridge configuration directs the power flow from the source to the load, while passively guaranteeing voltage limitation across each diode and switch, and providing volts-seconds balance for the resonant inductor Lr.

Methods and circuits for measuring the conductivity of solutions

Abstract: Improved circuits for measuring the conductivity of a solution confined between two electrodes in a cell compensate for series capacitance and parallel capacitance between the electrodes. A bipolar square-wave signal is applied to the cell. In one embodiment, the current through the cell is measured by an op-amp in current-to-voltage converter configuration. A feedback resistance employed with the op-amp in a feedback loop is controlled to a low value to ensure that the parallel capacitance is fully charged during an initial portion of each half-cycle of the drive signal. The feedback resistance is then selected so that the gain of the feedback loop is responsive to the range of the resistivity of the solution, and the measurement is made. In a further embodiment, charge proportional to the current through the cell is integrated across the op-amp, and the rate of charge is measured by measuring the time required to integrate the current to a predetermined level, and used to determine the resistivity of the solution. In this embodiment, the parallel capacitance is fully charged before each integration period begins. The voltage developed across the series capacitance is constant and can be compensated mathematically.

Capacitive electrode system for detecting open solder joints in printed circuit assemblies

Abstract: Disclosed is a system that determines whether input and output leads of semiconductor components are present and properly soldered to a printed circuit board. The system includes a signal source which is connected to a wiring trace on the printed circuit board, which is soldered to the lead being tested. A capacitive test probe is placed on top of the component and connected to a capacitance measuring device. The signal source signal is capacitively coupled through the lead of the integrated circuit package being tested to the capacitive test probe, so if a predetermined capacitance is measured by the capacitance measuring device, the lead is connected to the circuit assembly. As the capacitances being measured are small, the capacitive test probe may include an amplifier, a shield or a buffer circuit to reduce stray capacitance.

Measurements of optical‐heterodyne conversion in low‐temperature‐grown GaAs

Abstract: A low‐temperature‐grown GaAs interdigitated‐electrode photomixer is used to generate coherent power at microwave frequencies. An output power of 200 μW (−7 dBm) is generated by pumping the photomixer with two 70‐mW modes of a Ti:Al2O3 laser, separated in frequency by 200 MHz. This represents an optical‐to‐microwave conversion efficiency of 0.14%, which is within 50% of a prediction based on optical‐heterodyne theory. When two lasers are used and the frequency of one is tuned with respect to the other, the output frequency of the photomixer increases smoothly and the output power is nearly constant up to 20 GHz. At higher frequencies the power decays because of parasitic capacitance.

Nonlinearity of p-i-n photodetectors

Abstract: At higher operating frequencies, the field dependence of the carrier velocity in p-i-n photodetectors generates harmonics and intermodulation products that can degrade the dynamic range of RF fiber-optic links. The authors present both a perturbational theory and measured harmonic data for a p-i-n photodiode operated at very high power densities which show that this and other detector nonlinear effects need not seriously compromise link performance. In particular, neither transit-time nor static nonlinearities in p-i-n photodiodes need limit the dynamic range of fiber-optic links operating below 5 GHz. The fact that the theoretical bandwidth of the photodiode, with all parasitic capacitance and inductance ideally removed, is 17 GHz, suggests that comparable spur-free performance should be achievable at X and Ku-band frequencies, once packaging parasitics are reduced. >

Capacitance of disk capacitors

Abstract: The capacitance of a parallel-plate capacitor is formulated in basic electrostatics, assuming that the separation between the two electrode plates is very narrow and the fringe field of the edges is negligible. However, in practical problems of electrical and electronic engineering there are many cases where the plate separation is wide and the fringe field effect cannot be neglected. In the authors' previously published paper the capacitance of strip capacitor was computed by the boundary element method (BEM) for the case where the separation becomes wide, and a new empirical formula of the capacitance against the plate separation was derived. The empirical formula agreed well with experimental data. A formula for the capacitance of a parallel plate disk capacitor is presented. The formula is valid over a wider separation than formulas presented previously. As a special case of the problem, the capacitance of parallel plate ring capacitors is computed by the BEM. >

Capacitive pressure sensor having circuitry for eliminating stray capacitance

Abstract: A pressure sensor measures pressure by measuring capacitance between two capacitive plates. Pressure change appears as a change in capacitance. Stray capacitance interferes with this measurement. The stray capacitance arises between the capacitor plates and surrounding material. Circuitry reduces stray capacitance by maintaining substantially no potential difference between a capacitor plate and surrounding material responsible for stray capacitance.

An 86-106 GHz quasi-integrated low noise Schottky receiver

Abstract: An integrated planar receiver has been developed and tested over the 82-112 GHz bandwidth. The quasi-integrated antenna used in the receiver has a high gain, a high Gaussian coupling efficiency and a wide bandwidth. The mixer design consists of a planar GaAs Schottky diode placed at the feed of a dipole probe suspended inside an integrated horn antenna. The diode uses an etched surface channel and a planar air bridge for reduced parasitic capacitance. At 92 GHz, the room temperature antenna-mixer exhibits a double sideband (DBS) conversion loss and noise temperature of 5.5+or-0.5 Db and 770 K+or-50 K, respectively. The measured DSB conversion loss, and noise temperature over a 20-GHz bandwidth (86-106 GHz) remain less than 6.2+or-0.5 dB and 1000 K+or-50 K, respectively. The low cost of fabrication and simplicity of the design makes it ideal for millimeter- and submillimeter-wave receivers. >

Printed circuit board having integrated decoupling capacitive core with discrete elements

Abstract: A printed circuit board laminate is disclosed having a high capacitance power distribution core. The power distribution core comprises a pair of conductive plates electrically connected to an array of high capacitance core tiles, separated by a compliant dielectric filler. The resulting capacitance of the power distribution core is sufficient to eliminate the need for decoupling capacitors on a typical printed circuit board. Separate power supply areas of variable decoupling capacitance can be formed for mounted integrated circuits with different power supply requirements. A method for manufacturing such board laminates is also disclosed that is compatible with standard printed circuit board assembly technology.

Integral decoupling capacitance reduces multichip module ground bounce

Abstract: A multichip module technology in which the module's power planes cover the entire module surface and are separated by 0.15- mu m of anodized aluminum (Al/sub 2/O/sub 3/) is discussed. The module provides 50 nF/cm/sup 2/ decoupling capacitance across the power supply planes with negligible series inductance. The large capacitance eliminates the need for most if not all discrete capacitors, thereby saving space, reducing delays and increasing packing density. The negligible inductance yields modules having less inductive voltage drop between power levels than any equivalent module relying on discrete decoupling capacitors. >

Low power driver circuit for an AC plasma display panel

Abstract: The present invention provides a novel energy recovery circuit for an AC plasma display device. The circuit includes a series connection of a load capacitance in a display panel, an inductor to recover most of energies normally lost in charging and discharging the load capacitance and a two way switching device comprising a pair of n-channel MOS transistors connected in series to each other so that a line, on which charging and discharging current flow, includes no diode nor resistive element thereby the circuit is free from any unnecessary parasitic capacitance.

Active matrix liquid crystal display

Abstract: A parasitic capacitance is not caused between a shielding film and a gate line and between a pixel electrode and the gate line in a liquid crystal display of the present invention because the shielding film and the pixel electrode do not overlap the gate lines. The display characteristics are thus improved. Furthermore, since the counter shielding film is formed so as to cover a smaller gap of one between the shielding film and the gate line and one between the gate line and pixel electrode, light leak through the gap can be blocked. The shielding film can be small because it only covers the gap, thereby preventing a degradation of an aperture ratio. Moreover, a degradation of yield caused by increasing a number of production steps is also prevented because the production steps are not complicated. In another aspect of the liquid crystal display of the present invention, since the gate line is electrically connected to a counter electrode, a part of the parasitic capacitance caused between the pixel electrode and the shielding film end between the pixel electrode and the gate line is connected in parallel to a capacitance of liquid crystal and used as a storage capacitance. As a result, the parasitic capacitance less influences on the display characteristics, which is thus further improved. Further, since storage capacitance lines are not required, the aperture rate is not degraded and a degradation of yield caused by increasing a number of the production steps is prevented.

Class E full-wave low dv/dt rectifier

Abstract: An analysis and experimental verification for a Class E full-wave current-driven low dv/dt rectifier are given. Basic parameters of the circuit are derived using the time-domain analysis and Fourier series techniques. The rectifier diodes turn on and off at low dv/dt, yielding low switching noise and low switching losses. Diode parasitic capacitances do not adversely affect the circuit operation. The absolute value of di/dt is limited at diode turn-off, significantly reducing the reverse recovery current. The rectifier input voltage waveform differs only slightly from an ideal sinusoid, resulting in a low total harmonic distortion. The circuit has theoretically zero-ripple voltage and, therefore, zero loss in the equivalent series resistance (ESR) of the filter capacitor. The Class E full-wave topology has lower diode conduction loss than the Class E half-wave rectifier. The efficiency is almost constant over the load range from 10% to 100% of the full load. The rectifier offers high-power density and high-frequency rectification and is suitable for low-voltage and high-current applications, as shown by experimental results given for a 75-W rectifier which was operated at 1 MHz with an output of 5 V and 15 A. The theoretical and experimental results were in good agreement. >

Vibration sensitive isolation for printed circuit boards

Abstract: A printed circuit board includes vibration areas where vibration sensitive components of an electrical circuit design fabricated on the printed circuit board are mechanically isolated from supporting circuitry. The present invention provides a printed circuit board with areas having an increased natural resonant frequency of vibration for the circuit board area where the vibration sensitive circuit is located. The printed circuit board comprises a number of slots, holes or other openings around the vibration sensitive circuitry. In addition, one or more circuit board conductive paths are provided for maintaining electrical conductivity between the isolated circuit and the supporting circuits.

Power supply having a chopper with an improved power factor

Abstract: A power supply with a full-wave rectifier and a chopper having an inductor and a transistor connected in series across the rectifier. The transistor is switched on and off providing an interrupted voltage which is applied across a smoothing capacitor, via a blocking diode, to produce a smoothed DC voltage for driving a load. When the transistor is turned on, current from the rectifier is drawn through the inductor. When the transistor is turned off, the current through the inductor is conducted, in a positive direction, to the smoothing capacitor. The inductor and parasitic capacitance inherently present in the chopper create oscillations which allow current to flow through the inductor in a negative direction. A controller turns the transistor on at a time when the current flows in the negative direction and turns the transistor off after a predetermined on-period so as to release the current through the inductor, thereby causing the current to first flow in the negative direction and then in the positive direction through the inductor during the on-period. An input current wave shaping circuit is provided so that for each on-period, the amount of current flowing continuously through the inductor in the negative direction occurring immediately after the turning on of the transistor is less than the amount of current flowing through the inductor in the positive direction.

Inverter circuit for discharge tube

Abstract: PURPOSE:To miniaturize a step-up transformer by using a secondary side circuit as the feeder circuit of high frequency and employing parasitic capacitance as a part of a resonance circuit constituted between an inductive ballast and the inductive output of a leakage flux type transformer CONSTITUTION:A ballast is used as a choke coil from a conventional capacitor in an equivalent circuit, and the choke coil 2 of the secondary side circuit of a step-up transformer 1 has the effect of current limitation while a series resonance circuit is constituted with a parasitic capacitance 4 generated around a discharge tube 3, thus supplying the discharge tube 3 with high voltage When the parasitic capacitance 4 generated around the discharge tube 3 does not reach the calculated value of series resonance at that time, an auxiliary capacitance 5 is added in parallel, thus adjusting resonance frequency Accordingly, the parasitic capacitance is utilized as a part of the resonance circuit, thus adopting driving frequency higher than a conventional device, then miniaturizing the step-up transformer

Process of making self-aligned amorphous-silicon thin film transistors

Abstract: A thin film transistor structure and fabrication method for active matrix liquid crystal display. The structure is a self-aligned coplanar/staggered one. The feature of this structure is the self-aligned source and drain electrode to minimize the stray capacitance between the gate and the drain and the source. The source and drain electrodes are obtained by exposing negative photoresist on top of the transistor by incident light from the back of the transparent substrate using the gate electrode as a mask.

Layout scheme for precise capacitance ratios

Abstract: The present invention relates to the field of capacitor layout schemes for integrated circuits A method comprising nine specific layout criteria is disclosed that eliminates or greatly suppresses problems of prior art capacitance matching The nine layout criteria for providing precise capacitance ratios are: 1) fixed horizontal and vertical spacings are maintained for unit capacitors; 2) grounded dummy unit capacitors are placed around the periphery of each capacitor group; 3) two interconnects are used per unit capacitor; 4) equal numbers of top and bottom external interconnects per capacitance are maintained; 5) the external interconnect capacitance is made equal to the internal interconnect capacitance; 6) nonunit capacitors are used in the largest capacitance in a ratio; 7) the top plate interconnect of a capacitance is isolated from the bottom plate interconnect of the same capacitance; 8) interconnects are shielded from opposite capacitor plates; and, 9) rows of unit capacitors of the same capacitance are isolated from each other This layout scheme provides improved accuracy and reproducibility for capacitance matching in silicon integrated circuits Another advantage of this method is that, by limiting the options available for laying out matched capacitor structures, the layout process is streamlined in a manner that reduces time and, in particular, lends itself to automation Still another advantage of it is that less space is required for the same circuit in most cases

Logic simulation apparatus and circuit simulation apparatus

Abstract: There are provided a logic simulator apparatus and a circuit simulation apparatus capable of simulation based on signal propagation delay time with high reliability. A voltage drop calculating portion (9) calculates a voltage drop value (Vi) on the basis of power-supply information (D4), drain current (Ii) and voltage drop resistance (Ri). A propagation delay calculating portion (10) calculates delay time (Di) required for each element to propagate a logic signal value on the basis of gain coefficient (βi), interconnection parasitic capacitance (Cj) and voltage drop value (Vi). A logic simulation performing portion (12) performs the logic simulation on the basis of the circuit connection data (D22) provided with the delay time (Di). Accordingly, logic and circuit simulation can be accomplished on the basis of the signal propagation delay time with high reliability.

Semiconductor device and liquid crystal display.

Abstract: PURPOSE:To enable stable and rapid driving step of the title semiconductor device and liquid crystal display to be performed by a method wherein an electrode lead-out part is provided in the channel region of a MOS transistor to control the potential for using a high power supply voltage. CONSTITUTION:A gate wiring 4 of a PMOS transistor 11 and another gate wiring 9 of an NMOS transistor 12 are connected to an input terminal 15 at a gate connection part 16. The electrode lead-out part 5 in the channel region of the PMOS transistor 11 is connected to a VDD terminal 13 while the other electrode lead-out part 10 in the channel region of the NMOS transistor 12 is connected at a VSS terminal 14 so as to control the potential of respective channel regions. Through these procedures, the electrode lead-out parts 5, 11 are provided so that the breakdown voltage of the NMOS transistor 12 can be boosted while avoiding the threshold value voltage shifting due to the difference in bias potential. Resultantly, the driving step by a power supply voltage of 14V can be performed. Furthermore, the parasitic capacitance can be decreased to make the complete depletion feasible thereby enabling the impurity concentration to be lowered for increasing the hole mobility and the driving power.

Switched-capacitor chaotic neuron for chaotic neural networks

Abstract: A switched capacitor implementation of a neuron model which exhibits chaotic behavior is presented. The model is based on the experimentally observed characteristics of a squid neuron. It is shown that the proposed circuit qualitatively replicates the response of the real neuron by extensive simulations using SWITCAP2 and simulated program with IC emphasis (SPICE). Various nonideal effects such as DC gain, input offset voltage, and parasitic capacitances associated with SC implementation are investigated and the operational amplifier offset voltage is identified as a major problem. An existing offset voltage compensation scheme is adopted to alleviate the problem. >

Voltage programmable links programmed with low current transistors

Abstract: An electrical path can be formed through a transformable insulator between first and second conductors by applying a voltage between such conductors across at least one selected region of the insulator. Much of the current required to complete the link is provided from parasitic capacitance of the writing circuit or from capacitance which is removable from the circuit during normal operations. As a result, small transistors of less than 100 microamps may be used in the writing circuit which applies the programming voltage.

Symmetric differential capacitive pressure sensor

Abstract: Differential capacitive sensors are common to pressure gauges. Previous sensors of the bridge type have utilized only two variable (active) components, resulting in a half‐bridge electrical equivalent circuit. There are numerous advantages of a symmetric full bridge, using four active components. The symmetry improves linearity and increases signal to noise ratio, especially when supported by electronics based on synchronous detection. Another advantage of symmetry is invariance to scaling, through immunity to stray capacitance. This feature is especially important in relationship to the current trend toward micro‐electro‐mechanical systems. A crude, inexpensive, macroscopic prototype of the present design was built with attention to high sensitivity. Constructed with a thin aluminized Mylar diaphragm, this device can readily resolve pressure changes smaller than 10−2 Pa.

Digital cancellation of noise and offset for capacitive sensors

Abstract: A digital noise and offset cancellation technique for use with charge-redistribution capacitance sense techniques is presented. It is insensitive to parasitic capacitances, and can cancel the effects of offsets, low-frequency noise sources, and sampled kT/C noise of the MOS switch used in the topology. It represents a significant improvement in capacitance resolution than previous methods. It is currently being used in the readout circuits of experimental pressure sensor chips containing 100 fF air-gap capacitors with a resolution in the 30 aF range at a sampling speed of 11 kHz. >

Capacitor array digital/analog converter with compensation array for stray capacitance

Abstract: A digital/analog converter with a weighted capacitive converter network is provided with weighted stray capacitors for reducing non-linearities in switching. Additional stray capacitors are connected in parallel to the otherwise present stray capacitors for that purpose. In the higher-value network capacitances, the additional stray capacitors are positive, in the lower-value network capacitances, the stray capacitors are effective, i.e. their effect is negative. The converter is constructed differentially in its entirety. The combination allows the optimization with regard to the chip surface.

Novel 18/36 GHz (M)MIC GaAs FET frequency doublers in CPW-techniques under the consideration of the effects of coplanar discontinuities

Abstract: The design and performance of single-device and balanced versions of (M)MIC GaAs FET frequency doublers from 18 GHz to 36 GHz, fabricated in purely coplanar waveguide techniques, are presented. Coplanar discontinuities which are usually neglected are taken into consideration in the analysis and design. Spiral inductors and their associated parasitic capacitance are used for impedance matching and phase shifting purposes. The simulation technique used to characterize the spiral inductors is described in detail. Measurement and simulation results show good agreement. The investigated hybrid doublers have a minimum conversion loss of 7 dB while a maximum conversion gain of 6B is predicted for the monolithic version of the doublers. They are fabricated on ceramic and gallium arsenide substrates and are simple, cost effective, and applicable in low and medium power transmitter/receiver systems. >