Showing papers on "Phase detector published in 2001"

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector

Abstract: A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology in an area of 1.1/spl times/0.9 mm/sup 2/, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28/spl times/10/sup -6/, with random data input of length 2/sup 23/-1. The power dissipation is 72 mW from a 2.5-V supply.

Delay locked loop

Abstract: PURPOSE: A delay locked loop(DLL) is provided which to assure a wider locked range in a limited layout area and to minimize jitter. CONSTITUTION: A voltage generator(21) generates the first and the second voltage having different potentials. The first phase detector(24) detects a phase difference between a reference clock(refCLK) and an internal clock(intCLK), and outputs an enable signal. The first shift register(25) outputs the first control signal after shifting in response to a phase detection signal from the first phase detector. The first delay line unit(22) outputs a clock(CLK) by delaying the reference clock according to the first voltage and the first control signal. The second phase detector(26) detects a phase difference between the reference clock and the internal clock according to an enable signal from the first phase detector. The second shift register(27) outputs the second control signal after shifting in response to a phase detection signal from the second phase detector. And the second delay line unit(23) outputs an internal clock by delaying the above clock from the first delay line unit according to the second voltage and the second control signal.

Phase locked loop employing a fractional frequency synthesizer as a variable oscillator

Abstract: A phase locked loop (PLL) circuit is disclosed comprising a phase detector for generating a phase error between an input oscillating signal and an output oscillating signal. A fractional frequency synthesizer (FFS) generates the output oscillating signal in response to the phase error, wherein the FFS comprises an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr. The variable I is an integer value, and the variable Fr is a fractional value, both of which are generated in response to the phase error.

Analog frequency modulation detector for dynamic force microscopy

Abstract: A new analog frequency modulation (FM) detector (demodulator) for dynamic force microscopy (DFM) is presented. The detector is designed for DFM by utilizing the FM detection method where the resonance frequency shift of the force sensor is kept constant to regulate the distance between a tip and a sample surface. The FM detector employs a phase-locked loop (PLL) circuit using a voltage-controlled crystal oscillator (VCXO) so that the thermal drift of the output signal is negligibly reduced. The PLL is used together with a frequency conversion (heterodyne) circuit allowing the FM detector to be used for a wide variety of force sensors with the resonance frequency ranging from 10 kHz to 10 MHz. The minimum detectable frequency shift was as small as 0.1 Hz at the detection bandwidth of 1 kHz. The detector can track a resonance frequency shift as large as 1 kHz. We also present some experimental results including the observations of the Si(111)-7×7 reconstructed surface and fullerene molecules deposited on the surface by DFM using this FM detector.

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

Abstract: This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-/spl mu/m digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8/spl times/0.4 mm/sup 2/.

Digitally-synthesized loop filter circuit particularly useful for a phase locked loop

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block. Consequently, an increasingly larger equivalent capacitor may be implemented by adding additional digital stages, each of which requires a small incremental integrated circuit area. The power dissipation of the digital integration block is reduced by incorporating a decimation stage to reduce the required operating frequency of the remainder of the digital integration block.

A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition

Abstract: A digitally controlled phase-locked loop (DCPLL) that achieves fast acquisition by employing a digital phase-frequency detector (DPFD) and a variable loop gain scheme was developed for an advanced clock synthesizer and was fabricated in a 3.3-V 0.6-/spl mu/m CMOS process. The DPFD was developed to measure the frequency difference and to generate digital outputs corresponding to the difference. Using these features, the DCPLL achieves ideally one-cycle frequency acquisition when programmed with an appropriate gain. The experimental results show that the fabricated DCPLL exhibits three-cycle and one-cycle frequency acquisitions, when locking to 400 MHz (VCO at 800 MHz) and 200 MHz (VCO at 400 MHz), respectively.

Digital phase lock loop

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal. The digital frequency synthesizer also a non-glitching MUX electrically coupled to the digital DLL for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse glitch-free from the selected output tap, and a phase accumulator electrically coupled to the non-glitching MUX for precisely dividing a timing period of the input reference signal and for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse at a precise point in the timing period from the output tap. The digital phase detector, is electrically coupled to the digital frequency synthesizer to compare an edge of the input reference signal to an edge of a synthesized signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the synthesized signal.

Fourier transform method for self-mixing interference signal analysis

Abstract: Self-mixing interferometry (SMI) has been used to measure the distance and displacement. Although the principle of self-mixing interference is different conventional interference, we concluded that FFT analysis technique could also be used to detect the signal phase and increase the measurement precision of self-mixing interferometry. First the SMI signal is obtained by feeding the light from the target to cavity of laser diode, then it is pre-processed by an analog subtraction circuit to remove the overlapped output intensity due to the injection current modulation. Finally, SMI signal is analyzed by FFT phase detection method. Theoretical analysis and simulation calculations are presented. Experimentally, displacement of a PZT-driven target was measured with a precision of λ/50.

Phase-locked loop employing programmable tapped-delay-line oscillator

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step. The programmable loop filter is controlled to realize the selected loop filter and the selected loop filter is switched into a control loop involving the second phase detector. The control loop controls the oscillator to achieve phase lock by varying a supply voltage supplied to the oscillator.

A 10 Gb/s CMOS clock and data recovery circuit with frequency detection

Abstract: A 10 Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. In 0.18 /spl mu/m CMOS technology, the circuit exhibits 1.43 GHz capture range and 0.8 ps rms jitter with length 2/sup 23/ PRBS. The power dissipation is 91 mW from a 1.8 V supply.

Clock recovery from 160 Gbit/s data signals using phase-locked loop with interferometric optical switch based on semiconductor optical amplifier

Abstract: Clock recovery from optical time division multiplexed data signals up to 160 Gbit/s is experimentally demonstrated using a phase-locked loop with a semiconductor optical amplifier in a loop mirror as a fast optical phase comparator. The timing jitter of the optical clock pulse extracted from a 160 Gbit/s data signal was <0.3 ps.

A 0.6-2.5 GBaud CMOS tracked 3/spl times/ oversampling transceiver with dead-zone phase detection for robust clock/data recovery

Abstract: For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase error. A tracked 3 /spl times/ oversampling technique with dead-zone phase detection is incorporated in the receiver for robust clock/data recovery in the presence of excessive jitter and intersymbol interference (ISI). Due to the dead-zone phase detection, phase adjustment is performed only on the tail portions of the transition histogram in the received data eye, thereby exhibiting wide pumping-current range, large jitter tolerance, and small phase error. A voltage-controlled oscillator (VCO), based on a folded starved inverter, shows about 50% less jitter than one with replica bias. The transceiver, implemented in 0.25-/spl mu/m CMOS technology, operates at 2.5 GBaud over a 10-m 150-/spl Omega/ STP cable and at 1.25 GBaud over a 25-m cable with a bit error rate (BER) of less than 10/sup -13/.

Phase and amplitude detector and method of determining errors

Abstract: This invention relates to a phase and amplitude detector ( 160 ) required to identify small signal errors in a signal envelope having a large dynamic range, especially in the context of linearization of a power amplifier ( 122 ) arrangement employing a pre-distortion technique. A vector generator ( 300, 352, 372 ) responsive to a reference signal R ( 110 ) produces a frame of reference vectors R 1 - R n ( 274-280 ) generated by a combination of the reference signal R ( 110 ) with first A ( 270 ) and second P ( 272 ) offset vectors that provide an amplitude and phase displacement of the reference signal R ( 110 ). A signal combiner ( 290-296, 360-366, 390-396 ) is arranged to generate difference vectors E 1 - E n by combining the frame of reference vectors R 1 - R n ( 274-280 ) and the feedback signal F ( 124, 150 ), with the difference vectors E 1 - E n expressing the phase (p, 254 ) and the gain (a, 252 ) error terms relative to the reference signal R ( 110 ) and the first A ( 270 ) and second P ( 272 ) offset vectors. An error signal detector, ( 330-336 ) responsive to the difference vectors E 1 - E n and arranged to provide a measure of the phase (p, 254 ) and the gain (a, 252 ) error terms, provides signal amplitudes that can be combined to generate error signals ( 182 (Y), 184 X)). The error signals take the general form: X=P 1 −P 2 −P 3 +P 4 =−8 P p R ; Y=P 1 +P 2 −P 3 −P 4 =−8 A a R

Phase-locked loop circuit and delay-locked loop circuit

Abstract: A PLL circuit and a DLL circuit able to stabilize a control voltage within a short time after a phase pull-in operation in each cycle of a reference clock. In a phase comparator, the size of a leading phase or a delayed phase of a feedback signal is detected with respect to a reference clock signa, and pulse signals having pulse widths corresponding to the size are output. A current corresponding to the signals is output from a charge pump circuit to a lag-lead filter, and a control voltage obtained by removing noise of the above output is output from a low-pass filter to a voltage-controlled oscillator. Furthermore, through capacitors, pulse signals are superposed on the control voltage, and a sharp waveform is obtained by correcting blunting of the waveform by the low-pass filter. Due to this, the control voltage is stabilized within a short time after a phase pull-in operation in each cycle of the reference clock signal.

Method and apparatus for demodulating coherent and non-coherent modulated signals

Abstract: A receiver (FIG. 3) receives FSK and coherent 8PSK protocols. A selectively configurable processor (20) demodulates the message signals, and includes a demodulator (50-58) that derives in-phase and quadrature signals based on the message signals. A phase detector (60-64) is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector (26) is responsive to the in-phase and quadrature signals to selectively connect a loop filter (66) between the phase detector and the demodulator. When the selector (26) connects the filter (66) between the phase detector (60-64) and demodulator (50-58), the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor (20) operates as a phase locked loop to demodulate coherent modulated signals. When the selector (26) disconnects the filter (66) from between the phase detector (60-64) and the demodulator (50-58), the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.

Design of carrier recovery algorithm for high-order QAM with large frequency acquisition range

Abstract: We propose a polarity decision carrier recovery algorithm that is useful for carrier acquisition in high order-QAM (quadrature amplitude modulation). The PD (phase detector) output and its variance characteristics are mathematically derived and the simulation results are presented. We design a carrier recovery loop with this polarity decision PD and ATC (automatic transfer-mode controller), which is proposed to detect a proper time for mode change and to yield fine phase tracking error in the steady state. While the conventional DD (decision directed) algorithm can only acquire frequency offsets of less than /spl plusmn/10 kHz, the proposed carrier recovery algorithm can acquire up to /spl plusmn/200 kHz without AFC (automatic frequency control). We show the RMS (root mean square) phase error performance using the proposed carrier recovery PLL (phase locked loop).

System and method for compensating for supply voltage induced signal delay mismatches

Abstract: Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.

An improved bang-bang phase detector for clock and data recovery applications

Abstract: A low power fully integrated PLL-based 5 Gb/s NRZ clock and data recovery circuit was successfully implemented in a 0.18 /spl mu/m CMOS process. A novel bang-bang phase detector, used in the implementation, resulted in improved jitter performance compared to conventional bang-bang detectors. Differential topologies were used for the charge-pump and VCO circuits to reduce the design sensitivity to power supply noise. The maximum measured clock jitter from a 2/sup 23/-1 pseudorandom bit stream (PRBS) input data was less than 4.8 ps rms. The total power dissipation was less than 80 mW from a 1.8 V supply.

Non-linear phase detector

Abstract: A non-linear phase detector includes a retiming stage and a phase synchronization stage. The retiming stage is coupled to a data signal and a recovered clock signal. The retiming stage is triggered by the recovered clock signal and samples the data signal to generate a retimed data signal and a clock synchronization signal. The phase synchronization stage is coupled to the retimed data signal and the clock synchronization signal. The phase synchronization stage is triggered by the retimed data signal and samples the clock synchronization signal to generate a phase control signal.

Inverter parallel operation system

Abstract: An inverter includes a DC power supply circuit, an inverter circuit having a plurality of switching elements and switching an output of the DC power supply circuit on the basis of a PWM signal to deliver a high-frequency voltage, a filter circuit converting the high-frequency voltage to a substantially sinusoidal AC voltage, a power detector detecting an effective or wattless power of the AC power, a phase angle calculator calculating a phase angle of current relative to voltage from the detected effective or wattless power, a phase detector detecting a leading or lagging state of the phase angle, and a controller decreasing a frequency of the output voltage when the phase detector detects the leading state of the phase angle, the controller increasing the frequency of the output voltage when the phase detector detects the lagging state of the phase angle.

Phase frequency detector circuit having reduced dead band

Abstract: A digital phase detector that conducts pump up and pump down control signals to a charge pump, wherein each of the control signals has pulses that have a substantially 50/50 duty cycle characteristic when the two input signals, i.e., the input data signal and the feedback clock signal, are substantially in phase. This substantially 50/50 duty cycle output reduces, if not eliminates, inherent problems related to the turn-on delays of the charge pump while maintaining a locked condition. The phase detector may further include an intelligence to detect and handle other situations, such as missing data pulses.

Delay locked loop "ACTIVE command" reactor

Abstract: A delay locked loop (DLL) that applies an amount of delay to an external clock signal to generate multiple delayed signals. One of the delayed signals is selected as an internal clock signal. The multiple delayed signals have different delays in relation to the external clock signal. If a change in operating condition of the DLL occurs, such as a change in the supply voltage during an operational mode of the memory device such as an ACTIVE, a READ or a REFRESH mode, the DLL immediately selects another delayed signal among the multiple delayed signals as a new internal clock signal to compensate for the change before a phase detector of the DLL detects the change.

A low jitter 125-1250 MHz process independent 0.18 /spl mu/m CMOS PLL based on a sample-reset loop filter

Abstract: This low-jitter high-resolution ripple-pole-less process-independent 0.18/spl mu/m CMOS PLL is based on a sample-reset loop filter technique. The key feature of this architecture is elimination of phase detector frequency spurs due to the ICO control current spikes during input phase difference. This is accomplished by averaging the charge injected by the proportional path over an entire input update period. As a consequence, the ICO control current has a shape characterized by a staircase of low amplitude steps, versus one characterized by narrow high amplitude pulses, and needs much less filtering for low-jitter operation.

A method for short or long range time-of-flight measurements using phase-detection with an analog circuit

Abstract: This paper describes a novel method to determine accurately the distance between a transmitting transducer and a receiving transducer in an ultrasonic ranging system (URS). The accuracy of the method is similar to that achieved by phase mea surement systems, which exhibit better accuracy than the conventional ranging systems that use magnitude thresholding to measure time-of-flight (TOF). Significant contributions of the method described here are that the maximum measurement range is not limited to one wavelength (or one period) of the acoustic wave used, and that the circuitry is very simple. A one-wavelength range limit is typical for phase-based ranging systems. The maximum range is limited only by the method used to measure TOF, which in our case was the maximum count of a 16-bit counter at 1 MHz clock rate. The method described uses simple analog circuitry to extract a digital pulse with a duration equivalent to the TOF. The prototype developed is very stable and robust, with an accuracy of /spl plusmn/0.295 mm. for a range of 0.5842 in (0.05%). This accuracy can be further improved by compensating for variations in the speed of sound due to temperature changes.

A high-resolution jitter measurement technique using ADC sampling

Abstract: In this paper, we propose a new technique for jitter measurement that can be implemented using commercially available, off-the-shelf components. The technique implements a high-resolution, high-speed, phase detector using a high-speed Analog-to-Digital Converter (ADC). The technique is shown to have high resolution and low test time compared to currently available techniques. Experimental results to demonstrate the effectiveness of the technique are presented.

Multiple input phase lock loop with hitless reference switching

Abstract: A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, includes an acquisition phase locked loop (PLL) for each input. The acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from the phase comparator. The first DCO of the acquisition PLL is in a feedback loop to supply an input to the phase comparator and the second DCO of the acquisition PLL has a control input to introduce a phase offset therein relative to said the DCO of the acquisition PLL and provides an output for the acquisition PLL. An output PLL has a phase comparator selectively connectable to the output of each of the acquisition PLLs. The output PLL has a first DCO providing an output for the circuit and a second DCO in a feedback loop providing a feedback signal to the phase comparator of the output PLL. The second DCO of the output PLL has a control input to introduce a phase offset therein relative to the first DCO of the output PLL. A control unit for sets the phase of the second DCO of the acquisition circuit and the second DCO of the output PLL to a common value during changeover from one input to another to avoid an instantaneous phase error upon switching reference signals.

Moisture detection apparatus and method

Abstract: A sensor to detect the presence of water or moisture in bulk materials includes a standard circuit board and a three element transmission line. The sensor electronics include an oscillator responsive to a direct current voltage supply which provides a square wave voltage signal. The sensor electronics further include a phase detector which detects the difference in phase between the reference square wave voltage signal and a signal provided to the transmission line buried in a medium. The phase difference is proportional to the dielectric constant of the medium surrounding the transmission line.

A difference detector PFD for low jitter PLL

Abstract: For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn't have any feedback path in phase frequency detector circuit, it can be operated up to 1.6 GHz. Furthermore, with difference detector, the dd-PFD has three states, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16 ps. The proposed PFD is designed using 0.35 /spl mu/m CMOS technology at 3.3 V power supply.

Symbol rate timing recovery for higher order partial response channels

Abstract: This paper provides a framework for analyzing and comparing timing recovery schemes for higher order partial response (PR) channels. Several classes of timing recovery schemes are analyzed. Timing recovery loops employing timing gradients or phase detectors derived from the minimum mean-square error (MMSE) criterion, the maximum likelihood (ML) criterion, and the timing function approach of Mueller and Muller (1976) (MRI) are analyzed and compared. The paper formulates and analyzes MMSE timing recovery in the context of a slope look-up table (SLT), which is amenable for an efficient implementation. The properties and performance of the SLT-based timing loop are compared with the ML and MM loops. Analysis and time step simulations for a practical 16-state PR magnetic recording channel show that the output noise jitter of the ML phase detector is worse than that of the SLT-based phase detector. This is primarily due to the presence of self-noise in the ML detector. Consequently, the SLT-based phase detector is to be preferred. In comparing the SLT and MM based timing loops, it is found that both schemes have similar jitter performance.