Journal ArticleDOI
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
J. Savoj,Behzad Razavi +1 more
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TLDR
In this article, a 10-Gb/s phase-locked clock and data recovery circuit with a half-rate phase detector was proposed. But the phase detector provided a linear characteristic while retiming and demultiplexing the data with no systematic phase offset, and the power dissipation was 72 mW from a 2.5V supply.Abstract:
A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology in an area of 1.1/spl times/0.9 mm/sup 2/, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28/spl times/10/sup -6/, with random data input of length 2/sup 23/-1. The power dissipation is 72 mW from a 2.5-V supply.read more
Citations
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Journal ArticleDOI
Challenges in the design high-speed clock and data recovery circuits
TL;DR: In this paper, the authors describe the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers, and present a number of architectures.
Journal ArticleDOI
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector
J. Savoj,Behzad Razavi +1 more
TL;DR: In this paper, a 10-Gb/s phase-locked clock and data recovery circuit incorporating a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming is presented.
Journal ArticleDOI
Analysis of the PLL jitter due to power/ground and substrate noise
TL;DR: A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed and a comparison between the results obtained by the mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.
Journal ArticleDOI
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator
TL;DR: A 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications that aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation so coupling between voltage-controlled oscillators in adjacent channels can be avoided.
Journal ArticleDOI
A 40 Gb/s clock and data recovery circuit in 0.18 /spl mu/m CMOS technology
Jri Lee,Behzad Razavi +1 more
TL;DR: The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs as mentioned in this paper.
References
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Journal ArticleDOI
A self correcting clock recovery curcuit
TL;DR: A new approach to the problem of extracting clock from NRZ data is described, both simple and self correcting, that holds the clock in the center of the data eye.
Journal ArticleDOI
A self correcting clock recovery circuit
TL;DR: A new approach to the problem of extracting clock from NRZ data is described, both simple and self correcting, that holds the clock in the center of the data eye.
Journal ArticleDOI
Design techniques for low-voltage high-speed digital bipolar circuits
Behzad Razavi,Y. Ota,R.G. Swartz +2 more
TL;DR: In this article, the authors describe design techniques for multigigahertz digital bipolar circuits with supply voltages as low as 1.5 V. Simulations on benchmarks such as frequency dividers and line drivers indicate that the proposed circuits achieve higher speed than their CMOS counterparts designed in a 0.5-/spl mu/m 12-GHz bipolar technology.
Journal ArticleDOI
SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application
Y.M. Greshishchev,P. Schvan +1 more
TL;DR: In this paper, an integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, it consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO), and a tri-state charge pump.
Journal ArticleDOI
Clock/data recovery PLL using half-frequency clock
TL;DR: A CMOS clock and data recovery PLL is described for serial nonreturn-to-zero (NRZ) data transmission and is error free up to 1.2 Gb/s with a 9-b pseudorandom data sequence.