Showing papers on "Physical design published in 2009"

What is Predictive Technology Model (PTM)

Abstract: The minimum feature size of CMOS technology will reach 10nm in ten years. Beyond that benchmark, the present scaling approach may have to take a different route. The grand challenge to integrated circuit design community is to identify alternative technologies, such as carbon-based electronics, integrate them into the circuit architecture, and enable continuous growth of chip scale and performance. Predictive Technology Model (PTM), which bridges the process development and circuit simulation through device modeling, is essential in assessing potentials and limits of new technology and in supporting early design prototyping.

Signal and Power Integrity - Simplified

Abstract: The #1 Practical Guide to Signal Integrity DesignNow Updated with Extensive New Coverage!This book brings together up-to-the-minute techniques for finding, fixing, and avoiding signal integrity problems in your design. Drawing on his work teaching more than five thousand engineers, world-class signal and power integrity expert Eric Bogatin systematically reviews the root causes of all six families of signal integrity problems and shows how to design them out early in the design cycle. This editions extensive new content includes a brand-new chapter on S-parameters in signal integrity applications, and another on power integrity and power distribution network designtopics at the forefront of contemporary electronics design.Coverage includesA fully up-to-date introduction to signal integrity and physical designHow design and technology selection can make or break the performance of the power distribution networkExploration of key concepts, such as plane impedance, spreading inductance, decoupling capacitors, and capacitor loop inductancePractical techniques for analyzing resistance, capacitance, inductance, and impedanceSolving signal integrity problems via rules of thumb, analytic approximation, numerical simulation, and measurementUnderstanding how interconnect physical design impacts signal integrityManaging differential pairs and lossesHarnessing the full power of S-parameters in high-speed serial link applicationsEnsuring power integrity throughout the entire power distribution pathRealistic design guidelines for improving signal integrity, and much moreUnlike books that concentrate on theoretical derivation and mathematical rigor, this book emphasizes intuitive understanding, practical tools, and engineering discipline. Designed for electronics industry professionals from beginners to experts it will be an invaluable resource for getting signal integrity designs right the first time, every time.

Analog Circuit Design in Nanoscale CMOS Technologies

Abstract: As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition Vsb > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as Vsb > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109 devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

Electronic Design Automation: Synthesis, Verification, and Test

Abstract: This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book. Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes Table of Contents Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

Integrated layout design of multi‐component system

Abstract: A new integrated layout optimization method is proposed here for the design of multi-component systems. By introducing movable components into the design domain, the components layout and the supporting structural topology are optimized simultaneously. The developed design procedure mainly consists of three parts: (i) Introduction of non-overlap constraints between components. The finite circle method (FCM) is used to avoid the components overlaps and also overlaps between components and the design domain boundaries. (ii) Layout optimization of the components and supporting structure. Locations and orientations of the components are assumed as geometrical design variables for the optimal placement while topology design variables of the supporting structure are defined by the density points. Meanwhile, embedded meshing techniques are developed to take into account the finite element mesh change caused by the component movements. (iii) Consistent material interpolation scheme between element stiffness and inertial load. The commonly used solid isotropic material with penalization model is improved to avoid the singularity of localized deformation in the presence of design dependent loading when the element stiffness and the involved inertial load are weakened by the element material removal. Finally, to validate the proposed design procedure, a variety of multi-component system layout design problems are tested and solved on account of inertia loads and gravity center position constraint. Solutions are compared with traditional topology designs without component. Copyright © 2008 John Wiley & Sons, Ltd.

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Abstract: Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of interconnect issues in 3-D circuits, is 3-D networks-on-chip (NoC). Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm silicon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, exploring several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures are reviewed as a promising solution for communication limited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits : Vertical integration is a novel communications paradigm where interconnect design is a primary focus

Abstract: Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of interconnect issues in 3-D circuits, is 3-D networks-on-chip (NoC). Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm silicon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, exploring several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures are reviewed as a promising solution for communication limited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.

High performance sub-system design and assembly

Abstract: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.

Methods and systems for computer aided design of 3D integrated circuits

Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies

Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

High-performance global routing with fast overflow reduction

Abstract: Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enhanced iterative negotiation-based rip-up/rerouting (INR). The prerouting employs a two-stage technique of congestion-hotspot historical cost pre-increment followed by small bounding-box area routing. The initial routing is based on efficient iterative monotonic routing. For traditional INR, it has evolved as the main stream for the state-of-the-art global routers, which reveals its great ability to reduce the congestion and overflow. As pointed out by recent works, however, traditional INR may get stuck at local optima as the number of iterations increases. To remedy this deficiency, we replace INR by enhanced iterative forbidden-region rip-up/rerouting (IFR) which features three new techniques of (1) multiple forbidden regions expansion, (2) critical subnet rerouting selection, and (3) look-ahead historical cost increment. Experimental results show that NTUgr achieves high-quality results for the ISPD'07 and ISPD'08 benchmarks for both overflow and runtime.

Essential Issues in Analytical Placement Algorithms

Abstract: The placement problem is to place objects into a fixed die such that no objects overlap with each other and some cost metric (e.g., wirelength) is optimized. Placement is a major step in physical design that has been studied for several decades. Although it is a classical problem, many modern design challenges have reshaped this problem. As a result, the placement problem has attracted much attention recently, and many new algorithms have been developed to handle the emerging design challenges. Modern placement algorithms can be classified into three major categories: simulated annealing, min-cut, and analytical algorithms. According to the recent literature, analytical algorithms typically achieve the best placement quality for large-scale circuit designs. In this paper, therefore, we shall give a systematic and comprehensive survey on the essential issues in analytical placement. This survey starts by dissecting the basic structure of analytical placement. Then, various techniques applied as components of popular analytical placers are studied, and two leading placers are exemplified to show the composition of these techniques into a complete placer. Finally, we point out some research directions for future analytical placement.

Modeling of layout-dependent stress effect in CMOS design

Abstract: Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90 nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45 nm node.

Cad flow for 15nm/22nm multiple fine grained wimpy gate lengths in sit gate flow

Abstract: Methods are described for forming an integrated circuit having multiple devices, such as transistors, with respective element lengths. The methods include a new CAD flow for producing masks used for exposing sidewall spacers which are to be etched to a smaller base width than other sidewall spacers and which in turn are used as an etch mask to form gate structures with smaller element lengths than those formed from the other sidewall spacers. Embodiments include generating a schematic of an integrated circuit and a corresponding netlist, establishing design rules for the integrated circuit, generating a computer aided design layout for the integrated circuit, plural transistors of the integrated circuit respectively having different gate lengths, checking the integrated circuit layout and netlist for compliance with the established design rules and for correspondence with the generated schematic, and generating a mask with different openings that correspond to the integrated circuit layout, in response to a satisfactory outcome of the checking step.

Design and Implementation of a Field Programmable CRC Circuit Architecture

Abstract: The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s.

Morphable DPU: Smart and efficient data path for signal processing applications

Abstract: A coarse grained morphable Datapath Unit (mDPU) has been proposed. This mDPU implements multiplier in a smart way that enables the component adders to be reused when we do not need the multiplier. A pipelined design further enhances the design by creating a balanced datapath in temporal sense. These two features results in a design that optimally uses silicon and time. A judicious set of Coarse Granular instructions are enabled by the mDPU that we show can implement typical signal processing functions. A radix-2 64 point FFT has been implemented in 90 nm technology using the proposed mDPUs and performance and energy results from physical design phase are reported and compared to a state-of-the-art comparable design from the research community. 4X improvement in performance and 2.5X improvement in power-performance product are reported.

Detecting context sensitive hot spots in standard cell libraries

Abstract: Advances in lithography patterning have been the primary driving force in microelectronics manufacturing processes. With the increasing gap between the wavelength of the optical source and feature sizes, the accompanying strong diffraction effects have a significant impact on the pattern fidelity of on-silicon layout shapes. Layout patterns become highly sensitive to those context shapes lying within the optical radius of influence. Under such optical proximity effects, manufacturability hot spots such as necking and bridging may occur. Studies have shown that manufacturability hot spots are pattern dependent in nature and should be considered at the design stage [1]. It is desirable to detect these hot spots as early as possible in the design flow to minimize the costs for correction. In this work, we propose a hot spot prediction method based on a support vector machine technique. Given the location of a hot spot candidate and its context patterns, the proposed method is capable of efficiently predicting whether a candidate would become a hot spot. It takes just seconds to classify thousands of samples. Due to its computational efficiency, it is possible to use this method in physical design tools to rapidly assess the quality of printed patterns. We demonstrate one such application in which we evaluate the layout quality in the boundary region of standard cells. In the conventional standard cell layout optimization process, lithography simulation is the main layout verification method. Since it is a very time-consuming process, the iterative optimization approach between simulation and layout correction [2] takes a long time and only a limited number of context patterns can be explored. We show that with the proposed hot spot prediction method, for each standard cell, a much greater context pattern space can be explored, and the context sensitivity of a hot spot candidate located near a cell boundary can be estimated.

Integrated front-end passive equalizer and method thereof

Abstract: A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit.

Relative positioning of circuit elements in circuit design

Abstract: Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.

Exact route matching algorithms for analog and mixed signal integrated circuits

Abstract: As SOC designs are getting more popular, the importance of design automation for analog and mixed-signal ICs is increasing. In this paper, we study the problem of exact route matching, which is an important physical design constraint commonly imposed on specific analog signals for the purpose of correct analog functionality. For this, we first propose a mathematical formulation that models the route matching problem exactly. Based on this formulation, we derive important theoretical conclusions, and propose dynamic-programming algorithms to solve the problem. We also discuss how to use heuristic search techniques to enable faster computations. Our experimental results show the effectiveness of our algorithms. Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuits]: Design Aids General Terms Algorithms, Design

Constraint-driven design: the next step towards analog design automation

Abstract: The design of analog circuits has historically been a time consuming, manual task. The stringent constraints that must be considered simultaneously make the task particularly difficult, and are a major reason analog design has often not been automated. We believe that constraint-driven design is a prerequisite to analog design automation as it enables expert knowledge to be included in the design flow. This paper provides an introduction to the concept of constraint-driven physical design. First, we identify the major challenges in analog physical design, which we show are mostly constrained-related. We then provide an overview of the essential components of a constraint-driven design methodology. Finally, we discuss the impact this approach has on the analog design flow and design algorithms.

Standard cell library and semiconductor integrated circuit

Abstract: A standard cell library for designing semiconductor integrated circuits in which the driving-force sequence of a cell having a single function is represented in the form of a geometric progression with a common ratio of “p-th root of 2” (p is a natural number of 2 or larger) and the layout of the transistors of an output signal driving unit of the cell is designed using only layout devices having limited sizes of the number p of permutation. Even if p is small, the driving-force sequence can be defined with very small steps of a geometric progression type and the sizes of the layout devices are discretely limited. Therefore, the accuracy of the performance model of the cell can be easily ensured, and the standard cell library enables a high performance circuit to be designed using a high reliable model. Therefore, the standard cell library equipped with a small-step driving-force sequence of a geometric progression type suitable for high performance circuit designing is devised with a discretely limited transistor size easily ensuring the accuracy of the performance model.

Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs

Abstract: Recent field-programmable gate array (FPGA) architectures are heterogeneous, owing to the presence of millions of gates in configurable logic blocks (CLBs), block RAMs, and multiplier blocks (MULs) which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithms for application-specific integrated circuits (ASIC) do not suffice. In this paper, we propose a three-phase algorithm for unified floorplan-topology generation and sizing on heterogeneous FPGAs. The method consists of a recursive balanced bipartitioning followed by the generation of slicing topologies and finally the allocation of CLBs and RAM/MULs to modules by a greedy heuristic and minimum-cost maximum-flow method, respectively. Experimental results on benchmark circuits show that our method HeteroFloorplan produces feasible floorplans within a few seconds with total half-perimeter wirelength (HPWL) improvement of 18%-52% over the very few previous approaches. We also compare our locally greedy CLB allocation with a network-flow formulation to establish its effectiveness.

An Improved Active Decoupling Capacitor for “Hot-Spot” Supply Noise Reduction in ASIC Designs

Abstract: On-chip decoupling capacitors (decaps) are widely used to reduce power supply noise by placing them at the appropriate locations on the chip between blocks. While passive decaps can provide a certain degree of protection against IR drop, if a problem is found after the physical design is completed, it is difficult to implement a quick fix to the problem. In this paper, we investigate the use of an active decap as a drop-in replacement for passive decaps to provide noise reduction for these so-called ldquohot-spotrdquo IR drop problems found late in the design process. A modified active decap design is proposed for ASIC applications operating up to 1 GHz. Our improvement uses latch-based comparators as the sensing circuit, which provides a better power/delay tradeoff than previous designs and incorporates hysteresis to minimize unnecessary switching. It is implemented in a 1 V-core 90 nm CMOS process with a total area of 0.085 mm2 and static power of 2.8 mW. Measurements from a number of test chips show that using an active decap can provide between 10%-20% noise reduction in the 200 MHz-1 GHz frequency range over its passive counterpart. Sizing and placement analyses are also carried out using circuit simulation. The active decap is most effective when placed in close proximity to the hot-spot, as compared to the passive decap which is less sensitive to the exact location. Overall, if sized and placed properly, active decaps can provide an additional 20% reduction in supply noise over passive decaps.

Method and apparatus for performing routing optimization during circuit design

Abstract: One embodiment of the present invention provides a system that concurrently optimizes multiple routing objectives during routing of an integrated circuit (IC) chip design. During operation, the system starts by receiving a routing solution for the IC chip design and a set of routing objectives. The system then partitions the IC chip design into a set of partitions. Next, for each partition in the set of partitions, the system optimizes the routing solution by, iteratively: (1) analyzing the routing solution to determine weights for the set of routing objectives; (2) constructing a cost function based on the weights for the set of routing objectives; and (3) modifying the routing solution within the partition to attempt to optimize the cost function.

Programmable Electrical Rule Checking

Abstract: Electrical rule checking techniques for analyzing integrated circuit design data to identify specified circuit element configurations. Both tools and methods implementing these techniques may be employed to identify circuit element configurations using both logical and physical layout information for the design data. A set of commands are provided that will allow a user to program a programmable electrical rule check tool to identify a wide variety of circuit element configurations, using both logical and physical layout data, as desired by the user.

Integrated electronics matching circuit at an antenna feed point for establishing wide bandwidth, low vswr operation, and method of design

Abstract: An integrated electronics matching circuit is placed directly at the feed points of an antenna to match a transmission line to the impedance of the antenna that results in preserving the originally-designed wide bandwidth of the antenna, which in one embodiment is 10:1. A methodology is provided for the design of the integrated electronics matching circuit that marries the output of an antenna modeling tool with an integrated circuit design tool, in which the S parameter outputs of the antenna modeling tool for the antenna ports are coupled to the corresponding ports of the integrated circuit designed by the integrated circuit design tool.