Showing papers on "Polycrystalline silicon published in 1972"

Diffusion of Impurities in Polycrystalline Silicon

Abstract: The diffusion of electrically active impurities into polycrystalline silicon deposited by the thermal decomposition of silane has been studied. Both boron and phosphorus have been found to diffuse more rapidly into polycrystalline silicon than into single‐crystal silicon. The diffusivity is greatest in films deposited at about 1000°C although this maximum is a function of the deposition rate, film thickness, and substrate material as well as the deposition temperature. The maximum diffusivity is associated with a structure which has the maximum {110} texture. Although most of the films have been deposited onto amorphous SiO2, a nucleating layer of polycrystalline silicon has been found to influence the diffusion of impurities into a thick layer of polycrystalline silicon deposited over the nucleating layer. An optimum structure is obtained with a nucleating layer containing maximum {110} texture. The enhanced diffusion is tentatively attributed to diffusion down defects in the polycrystalline silicon. The...

Field-effects in polycrystalline-silicon films

Abstract: The effect of a normal electric field applied near the surface of a chemically deposited, polycrystalline-silicon film has been studied. Since such polycrystalline films generally contain large numbers of deep donor and acceptor defect levels within the forbidden gap, an analysis of the effect of these deep defect levels has been performed. This analysis shows that deep donors increase the magnitude of the threshold voltage of a p -channel MOS transistor constructed with the conducting channel in the polycrystalline-silicon film, while deep acceptors have the opposite effect. The effects partially cancel when both types of defects are present. Experimental investigation of threshold voltages of p channel MOS transistors constructed in doped films indicates that the magnitude of the threshold voltage is increased by defect levels for both n - and p -type films. The effect is generally greates for films with minimum dopant concentration, in agreement with the expected behavior. Field-effect mobilities of approximately 30 cm 2 /V-sec are observed for most films. Films deposited at various temperatures over the range 650–1100°C with no intentional doping show that the magnitude of the threshold voltage generally decreases with increasing deposition temperature.

Measurement of Fracture Surface Energy of SiC

Abstract: The fracture surface energies of 5 polycrystalline silicon carbides were measured at room temperature using the double-cantilever-beam, notched-beam, and work-of-fracture methods. All methods yielded comparable fracture surface energies,

Methods of forming self aligned transistor structure having polycrystalline contacts

Abstract: Disclosed are three processes, which all employ a common sequence of steps, for forming discrete and integrtated circuit transistors having emitters self-aligned between base enhancements and various polycrystalline silicon contacting members. The first process forms transistors having polycrystalline emitter contacts. The second process employs anisotropic etching techniques for forming self-aligned, integrated circuit transistors having polycrystalline emitter and collector contacts along with shallow isolation and collector buried layer contacting diffusions. The third process provides a transistor having polycrystalline silicon contacts to the emitter and base enhancement regions and utilizes boron doped polycrystalline silicon base contacts as an etch stop.

Piezoresistive Properties of Polycrystalline Silicon Thin Film

Abstract: Intending to use semiconductor films for piezoresistive elements, polycrystalline silicon films are prepared by electron bombardment method on insulating substrates and electrical properties of the films are investigated. Gage factor of the film is in the vicinity of 25, temperature coefficient of resistance and gage factor is about 1.8×10-4/°C, 1.1×10-3, respectively, for the resistivity of an order of 10-3 Ω cm. Much smaller coefficients are obtained by heat treament.

Shielded silicon gate complementary MOS integrated circuit

Abstract: An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.

Method of forming silicon gate device structures with two or more gate levels

Abstract: Semiconductor device structures having multiple gate levels. The gate levels are composed of polycrystalline silicon. A single device may have two or more gate levels, separated by a dielectric, or different devices of a common structure may have differing threshold voltages by specific selection of particular polycrystalline silicon layers.

Method and material for passivating the junctions of mesa type semiconductor devices

Abstract: The method of producing mesa type semiconductor devices having passivated mesa junctions comprises the steps of providing a wafer having layers of P and N type semiconductor material deposited thereon removing semiconductor material from the layers at spaced intervals, preferably by etching, depositing high resistivity polycrystalline silicon material in the valleys created by removing the semiconductor material to passivate the mesa junctions and separating adjacent semiconductor devices by cutting through the wafer therebetween.

Method of making electrical contacts for and passivating a semiconductor device

Abstract: THE METHOD OF MAKING ELECTRICAL CONTACTS FOR AND PASSIVATING A SEMICONDUCTOR DEVICE INCLUDES THE STEPS OF DEPOSITING THEREOVER A LAYER OF POLYCRYSSTALLINE SILICON MATERIAL AND SELECTIVELY DOPING THE POLYCRYSTALLINE SILICON MATERIAL AT LOCATIONS WHEREAT THE ELECTRICAL CONNECTIONS ARE TO BE MADE TO RENDER IT CONDUCTIVE THEREAT. IN THE CASE OF SEMICONDUCTOR DEVICES HAVING A PASSIVATING LAYER OF SIO2 OR THE LIKE THEREOVER, THE SIO2 MUST FIRST BE REMOVED IN THOSE AREAS WHEREAT THE ELECTRICAL CONTACTS ARE TO BE FORMED.

Manufacture of bipolar semiconductor devices

Abstract: A method of making bipolar semiconductors in which the base contact regions and the emitter region are defined by one masking step. A layer of polycrystalline silicon is formed on a substrate, the polycrystalline layer being removed at the positions for the base contact regions and the emitter produced beneath the remaining part of the layer by diffusion from the polycrystalline silicon which has been doped with a suitable emitter region dopant.

Charge coupled device area imaging array

Abstract: A low light level self-scanned high resolution imaging array comprised of charge coupled devices. The charge coupled devices are used as either visible or IR sensors having a polycrystalline silicon transparent conductive gate electrode as well as a two phase stepped oxide aluminum electrode shift register. A unique cell geometry is disclosed together with its method of fabrication which is particularly adapted for an area array making possible low light level sensitivity with ''''blooming'''' suppression for use as a solid state TV camera. The entire signal processing and imaging is performed on a single semiconductor substrate preferably comprised of silicon.

I‐V characteristics of MOS capacitors with polycrystalline silicon field plates

Abstract: The I‐V characteristics of MOS capacitors utilizing polycrystalline p‐type silicon field plates were investigated. It was found that sizable current flow is observable in both directions under pulsed dc conditions at voltages much below those at which current flows under applied dc. This suggests that the polycrystalline silicon film can be driven into avalanche and thus inject electrons into the oxide as well as the single‐crystal Si wafer. Charge trapping during passage of avalanche injected currents was observed to occur principally at the silicon/oxide interfaces. The rate of trapping depended strongly on the boron content of the oxide.

Controlled loss capacitor

Abstract: A variable loss transmission line including conductive strips of polycrystalline silicon deposited on a substrate. The polycrystalline silicon is selectively doped with an impurity to vary the resistance of the strips, thereby varying the loss or attenuation characteristics of the transmission line.

Method of providing polycrystalline layers of elementtary substances on substrates

Abstract: A method of providing a polycrystalline layer of silicon on a silicon substrate having a surface oxide layer. A carrier gas containing a decomposable hydrogen compound of carbon or silicon is passed over the substrate while the substrate is heated at the decomposition temperature of the hydrogen compound, with the result that a dense nucleation layer is deposited. A reducible silicon compound is then introduced into the carrier gas in the presence of hydrogen to cause the silicon compound to be reduced releasing silicon which is deposited on the nucleation layer as a layer polycrystalline silicon which is even and uniform.

Semiconductor devices and method of manufacturing the same

Abstract: A semiconductor device wherein a polycrystalline silicon layer, conductively in contact with a source region and a drain region and having impurities of the same conductivity type as that of said source region and said drain region, is the lead out electrode of said source region and said drain region. The method of forming said semiconductor devices is also disclosed.

Process for making silicon metal

Abstract: THERE IS DESIRED AN IMPROVEMENT IN MAKING POLYCRYSTALLINE SILICON METAL, AS USED FOR THE MAKING OF SEMICONDUCTORS, FROM TRICHLOROSILANE WHICH INVOLVES PROVIDING GREATER AMOUNTS OF TRICHLOROSILANE IN A METAL FORMING REACTOR THEN HERETOFORE HAS BEEN EMPLOYED. THIS PROVIDES GREATER SI METAL PRODUCTIVITY THAN WAS HERETOFORE BELIEVED POSSIBLE.

Process for the formation of selfaligned silicon and aluminum gates

Abstract: A PROCESS FOR THE SIMULTANEOUS FORMATION OF SELFALIGNED SILICON GATES AND ALUMINUM GATES HAVING SELFALIGNED CHANNEL REGIONS ON THE SAME WAFER IS DISCLOSED. BASICALLY, THE PROCESS CONSISTS OF THE DEPOSITION OF SUCCESSIVE LAYERS OF SILICON NITRIDE AND POLYCRYSTALLINE SILICON OVER THICK AND THIN SILICON DIOXIDE REGIONS WHICH ARE DISPOSED ON THE SURFACE OF A SEMICONDUCTOR WAFER. POLYSILICON GATES ARE DELINEATED IN THE THIN OXIDE REGIONS. SUBSEQUENTLY, A CHEMICALLY VAPOR DEPOSITED SILICON DIOXIDE LAYER IS FORMED OVER THE SURFACE OF THE EXPOSED SILICON NITRIDE LAYER AND OVER THE POLYCRYSTALLINE SILICON GATE GEGIONS. AT THIS POINT, THE CVD OXIDE IS DELINEATED TO FORM AN OXIDE MASK WHICH WILL PERMIT THE REMOVAL OF SILICON NITRIDE DOWN TO THE THIN OXIDE AT CERTAIN REGIONS WHERE DIFFUSION WINDOWS ARE TO BE FORMED IN EXPOSED THIN OXIDE REGIONS WHICH ARE SUBSEQUENTLY REMOVED BY A DIP ETCH. WHILE THE EXPOSED THIN OXIDE REGIONS ARE MASKED BY EITHER SILICON NITRIDE PORTIONS OR POLYCRYSTALLINE SILICON GATE REGIONS, THE MASKING REGIONS OF CVD OXIDE WHICH PROTECTED THE SILICON NITRIDE LAYER ARE SIMULTANEOUSLY REMOVED BY THE DIP ETCH WHICH OPENS THE DIFFUSION WINDOWS IN THE THIN OXIDE REGIONS. AFTER A DIFFUSION STEP WHICH INCLUDES DEPOSITION OF A PHOSPHORUS DOPANT IN THE DIFFUSION WINDOWS FROM THE VAPOROUS PHASE AND A DRIVE-IN STEP, A THERMAL OXIDATION STEP IS CARRIED OUT WHICH COVERS THE DIFFUSED WINDOW REGIONS AND THE POLYSILICON GATES AND THICK OXIDE REGIONS LEAVING THE EXPOSED NITRIDE PORTIONS UNAFFECTED. IN A SUBSEQUENT MASKING STEP, DIFFUSION CONTACT WINDOWS AND SILICON GATES CONTACT WINDOWS ARE OPENED. THEN, METALLIZATION IS DEPOSITED EVERYWHERE AND DELINEATED TO FORM METAL GATES AND CONTACTS TO BOTH DIFFUSIONS AND SILICON GATES. METAL IS DELINEATED AND FORMED IN EACH OF THE EXPOSED SILICON NITRIDE REGIONS ONE OF WHICH IS A SELF-ALIGNED CHANNEL REGION FOR A METAL GATE FIELD-EFFECT TRANSISTOR. OTHER METAL GATES FOR A CHARGE COUPLED DEVICE ARE POSITIONED BY VIRTUE OF THE PRESENCE OF ADJACENT POLYSILICON GATES AND ARE INSULATED FROM THE SUBSTRATE BY A THIN OXIDE AND NITRIDE LAYER AND FROM THE SILICON GATES BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE ON THE SURFACE OF THE SILICON GATES. THE RESULTING STRUCTURE INCLUDES A METAL GATE FIELD-EFFECT TRANSISTOR, A SELF-ALIGNED SILICON GATE FIELD-EFFECT TRANSISTOR, AND A CHARGE COUPLED DEVICE ON THE SAME WAFER. BY USING AN ADDITIONAL MASKING STEP OVER THAT REQUIRED FOR THE FORMATION OF SILICON SELF-ALIGNED GATES ALONE, METAL GATES WHICH ARE EITHER SELF-ALIGNED BY VIRTUE OF ADJACENT POLYSILICON GATES OR BY VIRTUE OF THE PRESENCE OF A SELF-ALIGNED CHANNEL ARE THUS OBTAINED. IN ADDITION, A RANDOM ACCESS CHARGE COUPLED DEVICE WHICH INCORPORATES A METAL TRANSFER GATE AND A POLYSILICON STORAGE PLATE IS ALSO DISCLOSED. THE STRUCTURE RESULTS FROM THE ABOVE DESCRIBED FABRICATION PROCESS AND IS STRUCTURALLY UNIQUE IN THAT THE METAL GATE IS DISPOSED IMMEDIATELY ADJACENT TO A DIFFUSION REGION WHICH ITSELF IS DISPOSED UNDER A THICK OXIDE LAYER. IN ADDITION, THE POLYCRYSTALLINE SILICON STORAGE PLATE IS SPACED FROM THE METAL GATE BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE.

Method for fabricating polycrystalline structures for integrated circuits

Abstract: THE LAYER OF SEMICONDUCTOR MATERIAL UPON WHICH IT IS DEPOSITED BUT OPPOSITE THAT OF THE STRUCTURE TO BE ISOLATED, IT FORMS A GOOD ISOLATION MEMBER. VARIOUS PROCESSES ARE SHOWN FOR ADVANTAGEOUSLY FASHIONING POLYCRYSTALLINE SILICON STRUCTURES. AN IMPROVED INTEFRATED CIRCUIT STRUCTURE IS SHOWN HAVING AN INTEGRAL POLYCRYSTALLINE SILICON MEMBER. THE DOPING OF SUCH POLYCRYSTALLINE SILICON MEMBER CONTROLS TTHE USAGE OF SUCH MEMBER. WHEN THE POLY SILICON DOPING CHARACTERISTICS EQUAL THAT OF THE LAYER OF SEMICONDUCTOR MATERIAL UPON WHICH IT IS DEPOSITED, IT FORMS A GOOD CONDUCTOR AND IS USABLE AS A CONTACT. WHEN THE POLYCRYSTALLINE SILICON DOPING CHARACTERISTICS ARE AGAIN THE SAME AS THAT OF

Electrical Charactristics of Polycrystalline Silicon-Silicon Nitride-Silicon Dioxide-Silicon Structures

Abstract: The influences of annealing at high temperatures and of impurity diffusion such as phosphorus and boron on fast surface states and instabilities under bias-temperature treatment were investigated. The fast surface states and instabilities increased by annealing in nitrogen, argon and oxygen. The instabilities were caused by the increase in conductivity of silicon nitride films. It was supposed that during annealing, localized strains under polycrystalline silicon electrodes were absorbed by silicon nitride films which in turn underwent large deformation and became filled with high density traps responsible for the increase of conductivity of silicon nitride films. Annealing in hydrogen reduced fast surface states and improved the instabilities. These phenomena are explained by the elimination of traps on SiO2–Si interface and in the bulk of silicon nitride.

Semi-conductor substrates - coated with polycrystalline silicon and silicon dioxide by silane pyrolysis

Abstract: Thin polycrystalline Si films are a semi-conductor substrate in a hot-wall reactor by contacting substrate with SiH4 in a gaseous diluent and a gaseous vehicle at 600-700 degrees C. Vehicle may be fed to reactor at 25 l/min; mixt. of SiH4 + diluent at 2 (2.5) l/min and a nominal amt. specific resistance modifier, esp. NH3, at 40 cc/min. In a pref. process, a field effect transistor with Si control electrode is obtd. by (a) consecutively forming layers of Si3N4, Si and SiO2 on a semi-conductor substrate; (b) selectively removing Si3N4, Si and SiO2 layer from several zones with exposure of substrate zones; (c) removing SiO2 layer, (d) introducing interference materials of opposite conductivity into substrate zones and Si layer.

Dimensional-stability studies of candidate space-telescope mirror-substrate materials

Abstract: The effects of aging, vacuum exposure, and thermal cycling on the dimensional stability of mirror-substrate materials, fused silica, Cer-Vit, Kanigen-coated beryllium, polycrystalline silicon, and U.L.E. fused silica were investigated. A multiple-beam interferometer was used to determine nonrecoverable surface-shape changes of the 12.7-cm-diameter mirrors with substrates of these materials. Thermal cycling and aging in vacuum produced the largest changes, but only a few were as large as 1/30 wavelength, where the wavelength was 632.8 nm.