Showing papers on "Programmable logic device published in 2006"

Ultrahigh-speed reconfigurable logic gates based on four-wave mixing in a semiconductor optical amplifier

Abstract: We have demonstrated simple reconfigurable all-optical logic operations based on four-wave mixing in semiconductor optical amplifier and encoding information in the polarization of the input signals. Experimental implementation of six logic functions (including XOR, XNOR, AND, NOR, etc.) operating at 10 Gb/s were realized by simply adjusting two polarization controllers in the setup

Alterable application specific integrated circuit (ASIC)

Abstract: A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.

SEAT-LA: a soft error analysis tool for combinational logic

Abstract: Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft error rates (SER) in logic circuits. In this paper, we propose a new approach, which can be applied to designs that use cell libraries characterized for soft error analysis and utilizes analytical equations to model the propagation of a voltage pulse to the input of a state element. The average error of the SER estimates using our approach compared to the estimates obtained using circuit level simulations is 6.5% while providing an average speed up of 15000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

Look-up table based logic macro-cells

Abstract: A programmable look up table (LUT) structure that offers higher logic packing capacity over conventional LUT structures for programmable logic devices is disclosed. A programmable LUT structure comprising a first stage and one or more intermediate stages and a last stage, wherein at least one of said intermediate stages or the last stage further comprises: a primary input received in true and compliment logic levels, and an output; and two LUT values, said primary input coupling one of said LUT values to said output, wherein at least one of said LUT values further comprises: a secondary input and a configurable data value; and a programmable means to select either the secondary input or the data value as the LUT value.

A reconfigurable architecture for hybrid CMOS/Nanodevice circuits

Abstract: This report describes a preliminary evaluation of performance of a cell-FPGA-like architecture for future hybrid "CMOL" circuits. Such circuits will combine a semiconduc-tor-transistor (CMOS) stack and a two-level nanowire crossbar with molecular-scale two-terminal nanodevices (program-mable diodes) formed at each crosspoint. Our cell-based architecture is based on a uniform CMOL fabric of "tiles". Each tile consists of 12 four-transistor basic cells and one (four times larger) latch cell. Due to high density of nanodevices, which may be used for both logic and routing functions, CMOL FPGA may be reconfigured around defective nanodevices to provide high defect tolerance. Using a semi-custom set of design automation tools we have evaluated CMOL FPGA performance for the Toronto 20 benchmark set, so far without optimization of several parameters including the power supply voltage and nanowire pitch. The results show that even without such optimization, CMOL FPGA circuits may provide a density advantage of more than two orders of magnitude over the traditional CMOS FPGA with the same CMOS design rules, at comparable time delay, acceptable power consumption and potentially high defect tolerance.

Experimental Study of a Soft-Switched Isolated Bidirectional AC–DC Converter Without Auxiliary Circuit

Abstract: An isolated ac-dc converter topology includes a capacitively snubbered voltage source converter (VSC) and a cycloconverter, coupled by a medium frequency transformer. The topology offers the possibility of bilateral power flow as well as three-level pulse width modulation on the ac side. It is shown that by alternately commutating the VSC and the cycloconverter it is possible to achieve either zero-voltage or zero-current switching conditions for all semiconductor devices in all points of operation. This is the case without any need for auxiliary semiconductor devices. At low load the transformer current may be insufficient for recharging the VSC snubber capacitors. In this case, however, it is possible to utilize the cycloconverter for providing a current path by which a quasi-resonant commutation can be made. The design and operation of a 40-kVA prototype converter system is described. It is shown how the rather complex switching logic required for implementing the chosen algorithm for commutation and modulation can be realized by using modern programmable logic devices [field programmable gate array (FPGA)]. Measurement results from the prototype converter are presented and analyzed. The measurements indicate that the studied commutation algorithm works well in practice

3D Nanowire-Based Programmable Logic

Abstract: In nanowire-based logic, the semiconducting material (e.g., Si, GaN, SiGe) is grown into individual nanowires rather than being part of the substrate. This offers us the opportunity to stack multiple layers of nanowires to create a three-dimensional logic structure which has high quality semiconductors in all vertical layers. The authors detail a feasible three-dimensional programmable logic architecture which can plausibly be realized from layers of semiconducting nanowires, making only modest assumptions about the control and placement of individual nanowires in the assembly. This shows a natural path for continuing to scale areal logic density once nanowire pitches approach fundamental limits. The authors show that the three dimensional systems are volumetrically efficient, with the surface area reducing roughly in proportion to the number of vertical layers. The authors further show that, on average, delay is reduced 18% from compact layout in three dimensions. For only a 20% area impact, the authors show how to avoid adding any manufacturing steps to physically isolate portions of nanowire layers

Register retiming technique

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

System monitor in a programmable logic device

Abstract: Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic reconfiguration port.

Handling fatal computer hardware errors

Abstract: Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.

Introduction to Evolvable Hardware: A Practical Guide for Designing Self-Adaptive Systems

Abstract: PREFACE. ACKNOWLEDGMENTS. ACRONYMS. 1 INTRODUCTION. 1.1 Characteristics of Evolvable Circuits and Systems. 1.2 Why Evolvable Hardware Is Good (and Bad!). 1.3 Technology. 1.4 Evolvable Hardware vs. Evolved Hardware. 1.5 Intrinsic vs. Extrinsic Evolution. 1.6 Online vs. Offline Evolution. 1.7 Evolvable Hardware Applications. References. 2 FUNDAMENTALS OF EVOLUTIONARY COMPUTATION. 2.1 What Is an EA? 2.2 Components of an EA. 2.2.1 Representation. 2.2.2 Variation. 2.2.3 Evaluation. 2.2.4 Selection. 2.2.5 Population. 2.2.6 Termination Criteria. 2.3 Getting the EA to Work. 2.4 Which EA Is Best? References. 3 RECONFIGURABLE DIGITAL DEVICES. 3.1 Basic Architectures. 3.1.1 Programmable Logic Devices. 3.1.2 Field Programmable Gate Array. 3.2 Using Reconfigurable Hardware. 3.2.1 Design Phase. 3.2.2 Execution Phase. 3.3 Experimental Results. 3.4 Functional Overview of the POEtic Architecture. 3.4.1 Organic Subsystem. 3.4.2 Description of the Molecules. 3.4.3 Description of the Routing Layer. 3.4.4 Dynamic Routing. 3.5 Remarks. References. 4 RECONFIGURABLE ANALOG DEVICES. 4.1 Basic Architectures. 4.2 Transistor Arrays. 4.2.1 The NASA FTPA. 4.2.2 The Heidelberg FPTA. 4.3 Analog Arrays. 4.4 Remarks. References. 5 PUTTING EVOLVABLE HARDWARE TO USE. 5.1 Synthesis vs. Adaption. 5.2 Designing Self-Adaptive Systems. 5.2.1 Fault Tolerant Systems. 5.2.2 Real-Time Systems. 5.3 Creating Fault Tolerant Systems Using EHW. 5.4 Why Intrinsic Reconfiguration for Online Systems? 5.5 Quantifying Intrinsic Reconfiguration Time. 5.6 Putting Theory Into Practice. 5.6.1 Minimizing Risk With Anticipated Faults. 5.6.2 Minimizing Risk With Unanticipated Faults. 5.6.3 Suggested Practices. 5.7 Examples of EHW-Based Fault Recovery. 5.7.1 Population vs. Fitness-Based Designs. 5.7.2 EHW Compensators. 5.7.3 Robot Control. 5.7.4 The POEtic Project. 5.7.5 Embryo Development. 5.8 Remarks. References. 6 FUTURE WORK. 6.1 Circuit Synthesis Topics. 6.1.1 Digital Design. 6.1.2 Analog Design. 6.2 Circuit Adaption Topics. References. INDEX . ABOUT THE AUTHORS.

Semiconductor integrated circuit device

Abstract: A programmable logic device unit, a non-volatile memory unit which stores data for programming the programmable logic device unit in a part of data storage area thereof and a control circuit which controls the non-volatile memory unit to allow the data stored in a part of the data storage area to be read at power-on time and supplied to the programmable logic device unit are integrally provided on a semiconductor chip Based on the program data, the programmable logic device unit forms an interface for allowing the non-volatile memory unit to operate as at least one of a register, a flash memory, a random access memory, and a read-only memory

Specialized processing block for programmable logic device

Abstract: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.

Hardware/software co-design

Abstract: Reconfigurable hardware is becoming available with large enough capacity and performance to support complete systems. Field-programmable gate array (FPGA) and Programmable logic device (PLD) can be configured using software techniques not unfamiliar to software engineers working in the field of real-time systems. This chapter introduces the VHSIC hardware description language (VHDL) or Verilog languages other the context for their use, in the development of modern real-time systems. Systems-on-chip, using reconfigurable hardware in the form of FPGAs or complex programmable device (CPLDs), are becoming a popular form for embedded systems, often because of their reduced power requirements. This approach demands an integrated approach to hardware and software development if it is to be successful. Opportunities for all kinds of new applications will emerge using this cost-effective technology. FPGAs and PLDs can be configured using software techniques not unfamiliar to software engineers working in the field of real-time systems. The two most common hardware specification languages are VHDL in Europe and Verilog in the US.

Reconfigurable Asynchronous Logic

Abstract: Challenges in mapping asynchronous logic to a flexible substrate include developing a balance between circuit-level flexibility, mapping complexity, and logic overhead. We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture. The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs.

Designing via-configurable logic blocks for regular fabric

Abstract: In this paper, we describe the design process of a via-configurable logic block for regular fabric. The block consists of a via-configurable functional cell and two via-configurable inverter arrays. A via-configurable functional cell can efficiently implement most commonly used CMOS static cells, and a via-configurable inverter array is efficient in implementing inverters, repeaters, and some pass-transistor logic. The cells have prefabricated transistors, contacts, and M1 wires. The M2 mask is fixed. All of the functions can be realized by customizing only an M1-M2 via mask. We construct a general-purpose fabric based on the via-configurable block and show its great flexibility in implementing a variety of functions. Compared to other fabrics based on look-up tables or programmable logic arrays, our fabric has much higher performance, smaller area, and lower power consumption.

Reconfigurable logic structures

Abstract: Reconfigurable electronic structures and circuits using programmable, non¬ volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g. (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nanotube Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Apparatus and method for implementing an analog-to-digital converter in programmable logic devices

Abstract: An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.

Infrared camera electronic architectures

Abstract: In accordance with one or more embodiments of the present invention, an infrared camera includes an infrared detector providing infrared data and a programmable logic device providing timing and control signals to the infrared detector and processing the infrared data to provide an output signal based on the infrared data. Additional memory devices, if present, may be controlled by the programmable logic device, which manages the flow of information for the memory devices.

A QCA Implementation of a Configurable Logic Block for an FPGA

Abstract: This paper presents the design, layout, and successful simulation of a configurable logic block (CLB) for a field-programmable gate array (FPGA) architecture based on a next-generation technology, quantum-dot cellular automata (QCA). Previous work on QCA-based FPGAs has focused on programmable interconnect. In contrast, this paper focuses on programmable logic. A novel single-layer CLB with fixed interconnect is developed by implementing four look-up tables (LUTs). Also, this paper presents a novel serial write/random-access read QCA memory design, which is one of the components in a LUT. QCADesigner software is used to design and simulate a 4-to-16 decoder, 16-bit memory, and output circuit to implement a LUT. The simulation of the CLB confirms the expected outcomes.

Xilinx FPGA Based Multilevel PWM Single Phase Inverter

Abstract: In this paper a XILINX FPGA based multilevel PWM single-phase inverter was constructed by adding a bidirectional switch to the conventional bridge topology. The inverter can produce three and five different output voltage levels across the load. XILINX FPGA is a programmable logic device developed by XILINX which is considered as an efficient hardware for rapid prototyping. It is used as a PWM generator to apply the appropriate signals to inverter switches. In addition to XILINX FPGA, Matlab/Simulink software was used for simulation and verification of the proposed circuit before implementation, Simulation and experimental results show that both are in close agreement.

Method of securing programmable logic configuration data

Abstract: The present invention relates to a secure method of distributing configuration data for a programmable logic device (PLD). The configuration data is encrypted to generate encrypted configuration data. A decryption key is encrypted using a silicon key. The encrypted configuration data and the encrypted decryption key are transferred to a PLD. Within the PLD, the encrypted decryption key is decrypted using the silicon key. Then, also within the PLD, the encrypted configuration data is decrypted using the decryption key to recover the configuration data. The PLD is then configured using the configuration data. The silicon key may be communicated to the PLD by tying predetermined input pins to an active high voltage level or signal ground, to form a binary code.

Method and apparatus for securing a computer network

Abstract: In one embodiment, a network security appliance (100) includes a logic circuit (530), a network processing unit (110), and a general purpose processor (510) to protect a computer network from malicious codes, unauthorized data packets, and other network security threats. The logic circuit (530) may include one or more programmable logic devices configured to scan incoming data packets at different layers of a multi-layer protocol, such as the OSI-seven layer model. The network processing unit (110) may work in conjunction with the logic circuit (530) to perform protocol parsing, to form higher layer data units from the data packets, and other network communications-related tasks. The general purpose processor (510) may execute software for performing functions not available from the logic circuit or the network processing unit. For example, the general purpose processor (510) may remove malicious code from infected data or perform malicious code scanning on data when the logic circuit (530) is not configured to do so.

Thermal sensor allocation and placement for reconfigurable systems

Abstract: Temperature monitoring using thermal sensors is an essential tool for evaluating the thermal behavior and sustaining the reliable operation in high-performance and high-power systems. With current technology scaling and integration trends timely and accurate detection of localized heating will be evermore important. In this work, we address the creation of a resource efficient sensor infrastructure for computing systems that are of regular nature, such as logic array-based computing platforms. We propose algorithms to embed thermal sensors into a regular structure to minimize the number of sensors and determine sensor locations required to maintain a given accuracy in temperature sensing for a given design. Our algorithms are tailored for minimal usage of thermal sensors to suit a variety of architectural conditions. For programmable logic arrays the highly application-specific usage of the hardware resources leads to unpredictable thermal profiles. As a result, post-manufacture instantiation of thermal sensors is desired, which in turn demands the use of native hardware resources, which can be scarce. We demonstrate that using our techniques the number of sensors required to monitor a set of hotspots is reduced by 75% on an average, across different sizes of logic arrays for different hotspot distributions compared to a uniform distribution of sensors throughout the fabrics.

Structures and methods for implementing ternary adders/subtractors in programmable logic devices

Abstract: Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.

Adjustable transistor body bias circuitry

Abstract: An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals to minimize power consumption. The adjustable body bias circuitry can be controlled using programmable elements on the integrated circuit that are loaded with configuration data. The integrated circuit may be a programmable logic device integrated circuit containing programmable logic. The adjustable body bias circuitry can produce an adjustable negative body bias voltage for biasing n-channel metal-oxide-semiconductor transistors. The adjustable body bias circuitry contains a bandgap reference circuit, a charge pump circuit, and an adjustable voltage regulator.

Programmable logic circuit and method of using same

Abstract: A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at least one logic cell, columns and rows of wires coupled to the logic cell, and a programmable memory element located at the intersection of two wires. The programmable element acts as a switch and as memory for the logic circuit.

Topology aware mapping of logic functions onto nanowire-based crossbar architectures

Abstract: Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to build these architectures, regular nanowire crossbars are emerging as a promising candidate. While these regular structures resemble CMOS programmable logic arrays (PLAs), PLA logic synthesis methodologies fail to solve the associated problems since the length and connectivity constraints imposed by individual nanowires in these crossbars translate into challenges hitherto not considered. These strict topological constraints should be considered while mapping Boolean functions onto nanowire crossbars during logic synthesis. We develop a mathematical model for this problem, an algorithm to solve it and three heuristics to improve the algorithm runtime.

Apparatus and methods for adjusting performance characteristics of circuitry in programmable logic devices

Abstract: A programmable logic device (PLD) includes at least one general PLD circuit and at least one intellectual property (IP) block or circuit. The PLD further includes a power management circuit. The power management circuit is configured to control power to the PLD circuit and to the IP block.

Application specific instruction processor based implementation of a GNSS receiver on an FPGA

Abstract: In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in low-power, low-cost SoC for multioperable GNSS positioning is described, featuring sufficient computational power and flexibility. The central processing unit of the reconfigurable hardware macro is an ASIP accelerated by additional eFPGA and weakly configurable ASIC based co-processors. The different hardware building blocks (i.e. ASIP, eFPGA, ASIC) of the target architecture are motivated with state of the art GNSS receiver algorithms. To explore the design space of the target architecture and to develop appropriate partitioning cost functions a GNSS receiver testbed was realised on an FPGA board. The testbed utilises a programmable ASIP, designed and generated with the processor description language LISA, as a central processing unit. As a first accelerating co-processor the correlator was realised. Exemplary optimisations of the ASIP/co-processor architecture as well as the achieved improvements are described.