Showing papers on "Programmable logic device published in 2019"

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks

Abstract: In this paper, we propose a novel and SAT-resistant logic-locking technique, denoted as Full-Lock, to obfuscate and protect the hardware against threats including IP-piracy and reverse-engineering. The Full-Lock is constructed using a set of small-size fully Programmable Logic and Routing block (PLR) networks. The PLRs are SAT-hard instances with reasonable power, performance and area overheads which are used to obfuscate (1) the routing of a group of selected wires and (2) the logic of the gates leading and proceeding the selected wires. The Full-Lock resists removal attacks and breaks a SAT attack by significantly increasing the complexity of each SAT iteration.

Field Programmable Gate Array Applications—A Scientometric Review

Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

Petri Net-Based Specification of Cyber-Physical Systems Oriented to Control Direct Matrix Converters With Space Vector Modulation

Abstract: This paper proposes a Petri-net-based specification of cyber-physical systems dedicated to the control of a direct matrix converter with space vector modulation (SVM) and transistor commutation. The technique employed is further applied for hardware implementation in a programmable logic device [namely, field-programmable gate array (FPGA)]. Contrary to the traditional SVM computation methods, concurrency aspects of the digital devices are highly utilized in the presented solution. Therefore, the hardware system is specified by a live and safe Petri net, which is based on the parallelism. Moreover, such a specification can be easily analyzed and verified against the structural properties in order to avoid formal errors and prototyping mistakes (such as deadlocks or non-reachable states). The proposed idea is illustrated by a case-study example of the real prototype of the SVM algorithm. The system has been specified by a live and safe Petri net, analyzed, verified, and finally implemented in the FPGA device. The obtained results of the physical implementation are presented and discussed.

Generic Connectivity-Based CGRA Mapping via Integer Linear Programming

Abstract: Coarse-grained reconfigurable architectures (CGRAs) are programmable logic devices with large coarsegrained ALU-like logic blocks, and multi-bit datapath-style routing. CGRAs often have relatively restricted data routing networks, so they attract CAD mapping tools that use exact methods, such as Integer Linear Programming (ILP). However, tools that target general architectures must use large constraint systems to fully describe an architecture's flexibility, resulting in lengthy run-times. In this paper, we propose to derive connectivity information from an otherwise generic device model, and use this to create simpler ILPs, which we combine in an iterative schedule and retain most of the exactness of a fully-generic ILP approach. This new approach has a speed-up geometric mean of 5.88x when considering benchmarks that do not hita time-limit of 7.5 hours on the fully-generic ILP, and 37.6x otherwise. This was measured using the set of benchmarks used to originally evaluate the fully-generic approach and several more benchmarks representing computation tasks, over three different CGRA architectures. All run-times of the new approach are less than 20 minutes, with 90th percentile time of 410 seconds. The proposed mapping techniques are integrated into, and evaluated using the open-source CGRA-ME architecture modelling and exploration framework.

Open-Source RISC-V Processor IP Cores for FPGAs — Overview and Evaluation

Abstract: Advances in semiconductor miniaturization are an important driver for Field Programmable Gate Arrays (FPGAs) since their invention in the 1980s. The increasing number of available on chip logic resources on one hand and on the other hand a decrease in part costs let the FPGA market grow steadily in recent years. It comes thus at no surprise that more and more microprocessors are integrated into programmable logic devices as they represent the central functionality in many digital systems. In parallel to these technological developments the open-source hardware community grew steadily in the last two decades. More than hundred open-source CPU cores can thus be found and selecting a core for a design project has to be done with care. In this work we thus want to focus on open-source 32-bit CPU IP cores suitable for FPGAs and which support the upcoming free and open RISC-V instruction set architecture that has some interesting advantages when compared to commercial CPU cores (as will be outlined in the paper). An overview on available projects and activities will be given and evaluation results for a selection of cores will be presented.

MulNet: A Flexible CNN Processor With Higher Resource Utilization Efficiency for Constrained Devices

Abstract: Leveraging deep convolutional neural networks (DCNNs) for various application areas has become a recent inclination of many machine learning practitioners due to their impressive performance. Research trends show that the state-of-the-art networks are getting deeper and deeper and such networks have shown significant performance increase. Deeper and larger neural networks imply the increase in computational intensity and memory footprint. This is particularly a problem for inference-based applications on resource constrained computing platforms. On the other hand, field-programmable gate arrays (FPGAs) are becoming a promising choice in giving hardware solutions for most deep learning implementations due to their high-performance and low-power features. With the rapid formation of various state-of-the-art CNN architectures, a flexible CNN hardware processor that can handle different CNN architectures and yet customize itself to achieve higher resource efficiency and optimum performance is critically important. In this paper, a novel and highly flexible DCNN processor, MulNet, is proposed. MulNet can be used to process most regular state-of-the-art CNN variants aiming at maximizing resource utilization of a target device. A processing core with multiplier and without multiplier is employed to achieve that. We formulated optimum fixed-point quantization format for MulNet by analyzing layer-by-layer quantization error. We also created a power-of-2 quantization for multiplier-free (MF) processing core of MulNet. Both quantizations significantly reduced the memory space needed and the logic consumption in the target device. We utilized Xilinx Zynq SoCs to leverage the one die hybrid (CPU and FPGA) architecture. We devised a scheme that utilizes Zynq processing system (PS) for memory intensive layers and the Zynq programmable logic (PL) for computationally intensive layers. We implemented modified LeNet, CIFAR-10 full, ConvNet processor (CNP), MPCNN, and AlexNet to evaluate MulNet. Our architecture with MF processing cores shows the promising result, by saving 36%-72% on-chip memory and 10%-44% DSP48 IPs, compared to the architecture with cores implemented using the multiplier. Comparison with the state of the art showed a very promising 25-$40\times $ DSP48 and 25-$29\times $ on-chip memory reduction with up to 136.9-GOP/s performance and 88.49-GOP/s/W power efficiency. Hence, our results demonstrate that the proposed architecture can be very expedient for resource constrained devices.

Chaos-Based Physical Unclonable Functions

Abstract: The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs

Abstract: A logic synthesis for finite-state machines (FSMs) aimed at programmable array logic (PAL)-based complex programmable logic devices is proposed here. This approach consists of the simultaneous synthesis of a transition function and an output function. The main contribution is the novel multilevel optimization of an FSM. In this process, a new form of graph is used, i.e., a graph of excitations and outputs. This is a generalization of the graph of outputs that has previously been used in the process of technology mapping of multi-output functions in PAL-based programmable structures. The main idea, the theoretical background, and a precise algorithm are illustrated by means of simple examples. The proposed algorithm was compared with other approaches by synthesizing the FSM benchmarks and mapping the solutions to $k$ -term PAL-based logic blocks. The obtained results are compared on the basis of the area (number of logic blocks) and speed (number of logic levels). The proposed approach is especially effective for larger FSMs.

Exploring Zynq MPSoC: With PYNQ and Machine Learning Applications

Abstract: This book introduces the Zynq MPSoC (Multi-Processor System-on-Chip), an embedded device from Xilinx. The Zynq MPSoC combines a sophisticated processing system that includes ARM Cortex-A53 applications and ARM Cortex-R5 real-time processors, with FPGA programmable logic. As well as guiding the reader through the architecture of the device, design tools and methods are also covered in detail: both the conventional hardware/software co-design approach, and the newer software-defined methodology using Xilinx's SDx development environment. Featured aspects of Zynq MPSoC design include hardware and software development, multiprocessing, safety, security and platform management, and system booting. There are also special features on PYNQ, the Python-based framework for Zynq devices, and machine learning applications. This book should serve as a useful guide for those working with Zynq MPSoC, and equally as a reference for technical managers wishing to gain familiarity with the device and its associated design methodologies.

Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP)

Abstract: In this presentation I will present the new Adaptive Compute Acceleration Platform. I will show the overall system architecture of the family of devices including the Arm cores (scalar engines), the programmable logic (Adaptable Engines) and the new vector processor cores (AI engines). I will focus on the new AI engines in more detail and show the architecture, the integration in the total device, the programming environment and some applications, including Machine Learning and 5G wireless applications.

Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

Abstract: A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Lightweight True Random Bit Generators in PLDs: Figures of Merit and Performance Comparison

Abstract: We investigate and compare three low complexity circuit topologies to be implemented in programmable logic devices, for the design of True Random Bit Generators for Lightweight Cryptography. The architectures, based on the general idea of Digital Nonlinear Oscillators (DNOs), have been compared on the basis of measurement campaigns, carried out referring to figures of merit specifically introduced to assess the quality and reliability of the oscillators under test.

Impact of FPGA Architecture on Area and Performance of CGRA Overlays

Abstract: Coarse-grained reconfigurable arrays (CGRAs) are programmable logic devices with ALU-style processing elements and datapath interconnect. CGRAs can be realized as custom ASICs or implemented on FPGAs as overlays . A key element of CGRAs is that they are typically software programmable with rapid compile times – an advantage arising from their coarse-grained characteristics, simplifying CAD mapping tasks. We implement two previously published CGRAs as overlays on two commercial FPGAs (Intel and Xilinx), and consider the impact of the underlying FPGA architecture on the CGRA area and performance. We present optimizations for the overlays to take advantage of the FPGA architectural features and show a peak performance improvement of 1.93x, as well as maximum area savings of 31.1% and 48.5% for Intel and Xilinx, respectively, relative to a naive first-cut implementation. We also present a novel technique for a configurable multiplexer implementation, which embeds the select signals into SRAM configuration, saving 35.7% in area. The research is conducted using the open-source CGRA-ME (modeling and exploration) framework [1].

Low Power FPGA-SoC Design Techniques for CNN-based Object Detection Accelerator

Abstract: This paper shows the possibility of the existing low power register transfer level (RTL) techniques can be effective as a low power design scheme for CNN-based object recognition system acceleration in contrast to conventional techniques. Most power efficient design techniques regarding CNN acceleration are focused on the High-level Synthesis (HLS) aspect, such as memory bandwidth optimization, network architecture reconfiguration, data reuse, and batch normalization. However, these attempts have reached the limits of the effectiveness of itself. Using the post-synthesis RTL code generated by field-programmable gate arrays (FPGA) manufacturers, the proposed RTL low power design technique was applied to the original FIFO part for reducing the power consumption during data transformation. We compared the HLS optimized result with the RTL optimized result in the aspect of power consumption. We configured the testbench for the modified FIFO module and analyzed the estimated power dissipation result. These power effectiveness factors, such as a look-up table (LUT), a lookup table RAM (LUTRAM), can reduce the power dissipation by 54%, 49% respectively, even though increased block RAM (BRAM) leads to the elevated power dissipation by 154%. Thus, the total power consumption was able to be decreased by 10%. This paper discusses two factors of FPGA with system-on-chip (FPGA-SoC) design for CNN-based hardware implementation in power consumption aspect, such as RTL architecture, memory design architecture, and the model architecture-based hardware implementation methods. The virtual additional memory can support the high throughput at full speed. Our simulated low power schemes applied to Processing System (PS) and Programmable Logic (PL) architecture effectively reduced the power consumption by 25.9% in the FIFO data transformation. We established that the increased LUT blocks affect the power-efficient rate and reduce the power consumption of the PL design up to 49%.

Versal Network-on-Chip (NoC)

Abstract: Xilinx Versal Adaptable Compute Acceleration Platform (ACAP) is a new software-programmable heterogenous compute platform. The slowing of Moores law and the everpresent need for higher levels of compute performance has spurred the development of many domain specific accelerator architectures. ACAP devices are well suited to take advantage of this trend. They provide a combination of hardened heterogenous compute and IO elements and programmable logic. Programmable logic allows the accelerator to be customized in order to accelerate the whole application. The Versal Networkon-Chip (NoC) is a programmable resource that interconnects all of these elements. This paper outlines the motivation for a hardened NoC within a programmable accelerator platform and described the Versal NoC.

Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

Abstract: Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression’s construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.

Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board

Abstract: Due to the development of high-performance LSIs, autonomous vehicle will be realized in a few years. The FPGA Design Competition is one of the valuable opportunities to demonstrate an autonomous vehicle on miniature roads. In this paper, we develop a ROS-based autonomous vehicle which is implemented on an FPGA board as a mock car. ROS is a common framework designed to implement various types of robots. Utilizing the ROS-based platform, we develop a model car for the demonstration of an autonomous vehicle. The on-board programmable logic is used to off-load the processing of image recognition such as lane detection, traffic signal detection, and obstacle detection. The implementation results demonstrate that we can successfully implement essential components of the vehicle on an FPGA board with the ROS-based system.

MIGOU: A Low-Power Experimental Platform with Programmable Logic Resources and Software-Defined Radio Capabilities.

Abstract: The increase in the number of mobile and Internet of Things (IoT) devices, along with the demands of new applications and services, represents an important challenge in terms of spectral coexistence. As a result, these devices are now expected to make an efficient and dynamic use of the spectrum, and to provide processed information instead of simple raw sensor measurements. These communication and processing requirements have direct implications on the architecture of the systems. In this work, we present MIGOU, a wireless experimental platform that has been designed to address these challenges from the perspective of resource-constrained devices, such as wireless sensor nodes or IoT end-devices. At the radio level, the platform can operate both as a software-defined radio and as a traditional highly integrated radio transceiver, which demands less node resources. For the processing tasks, it relies on a system-on-a-chip that integrates an ARM Cortex-M3 processor, and a flash-based FPGA fabric, where high-speed processing tasks can be offloaded. The power consumption of the platform has been measured in the different modes of operation. In addition, these hardware features and power measurements have been compared with those of other representative platforms. The results obtained confirm that a state-of-the-art tradeoff between hardware flexibility and energy efficiency has been achieved. These characteristics will allow for the development of appropriate solutions to current end-devices’ challenges and to test them in real scenarios.

Logic drive using standard commodity programmable logic IC chips

Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

Study of the Data Exchange Between Programmable Logic and Processor System of Zynq-7000 Devices

Abstract: Zynq-7000 devices from Xilinx has gained strong popularity in the last years. Several documents and examples about interfaces usage and how to communicate the programmable logic with the processor are available, but some of them are not properly explained and in particular, the maximum throughput is not clearly specified. With this purpose, in this work a measurement method is presented and applied over the five available interfaces, considering the most used alternatives. Tests were carried on a Zybo board, but the results can be easily used to estimate the performance of others systems setups. Special hardware features and functionality are also discussed, providing a better understanding of system performance. Related papers were studied but none of them presents comparable information as to provide a fair comparison.

Four-Step Current Commutation Strategy for a Matrix Converter Based on Enhanced-PWM MCU Peripherals

Abstract: In this paper, an efficient implementation of the four-step current commutation technique for controlling bidirectional power switches in a Matrix Converter (MC) is proposed. This strategy is based on the enhanced pulse width modulation peripheral included in the C 2000 Delfino 32-bit microcontroller of Texas Instruments. By tuning the algorithmic parameters contained in this module, the four-step commutation process is carried out on the Microcontroller Unit (MCU) without overloading the full complex processor and avoiding the use of additional special hardware such as Field-Programmable Gate Arrays (FPGA) or Complex Programmable Logic Devices (CPLD) when controlling the MC. The algorithm is implemented on the TMS320F28379D MCU and operationally validated on an MC prototype, where the functionality of the proposal is demonstrated.

Compact electro-optical programmable logic device based on graphene–silicon switches

Abstract: A compact electro-optical programmable logic device (PLD) which can provide any of 16 possible minterms of four Boolean variables on an optical signal is demonstrated in this paper. The presented structure is based on electro-optical graphene–silicon switches that consist of a Mach–Zehnder interferometer in which a few-layer graphene is embedded in silicon slot waveguide to construct phase shifters. A large effective index variation can be achieved by embedding few-layer graphene inside the slot waveguide which enables us to have a compact footprint. Our analysis shows that the presented PLD has a small footprint of 1.86 × 1.28 mm2. Any combinational logic circuit can be implemented by programming the proposed PLD. Here, the presented structure is programmed to work under three different modes including logical operations, two-bit adder, and two-bit comparator with the advantage of very fast switching among operation modes. Comparison with previous works shows that our design has a compact footprint, high extinction ratio, and low insertion loss with broadband spectrum for wideband telecommunication.

Integral Remote laboratory for Programmable Logic

Abstract: The paper presents a new remote laboratory for the development of programmable logic experiments that allows to perform all the workflow included in the development of digital systems through programmable devices from an Internet browser.The architecture of the laboratory facilitates the deployment of multiple instances of experimentation that make possible the use of the laboratory in courses with numerous students.

Temperature distribution measurement based on field-programmable gate array embedded ring oscillators

Abstract: In this paper, a novel temperature distribution measurement method for packaged integrated circuit (IC) chips is proposed, based on field-programmable gate array (FPGA) embedded ring oscillators. A temperature sensing network is established using the programmable logic resources of the FPGA. Smart thermal sensors detect the temperature based on the relationship between the delay time and the temperature in the ring oscillators. An infrared image of the chip is captured using an infrared camera to verify the correctness of the proposed method. The spatial resolution of the temperature sensor network is 0.13 mm × 0.28 mm and the measured temperature error varies by less than 2.1 °C.

Modular Signal Processing Unit for Motion Control Applications Based on System-on-Chip with FPGA

Abstract: Motion control systems with distributed architecture where multiple input/output devices are connected to the upper layer controller by fast digital communication (fieldbus) became an industrial standard. This paper presents design of a modular input/output device which can process signals from multiple sensors, drive multiple actuators and act as a Slave or Master node in EtherCAT fieldbus network.User-defined algorithms can be easily implemented to preprocess input signals, combine multiple signals or close local control loops with extremely high sampling rates which makes the difference to standard off-the-shelf solutions. To meet these requirements and simplify hardware design, our device is based on System-on-Chip with both programmable logic (FPGA) and classic processor (CPU) ARM cores. Data processing including user algorithms can be done entirely in FPGA which provides very low latency and no jitter, and also on CPU for more complex computations with advantage of tight integration between FPGA and CPU. In this paper we provide description of hardware design, system architecture and typical applications.

Real-Time Implementation of Adaptive Correlation Filter Tracking for 4K Video Stream in Zynq UltraScale+ MPSoC

Abstract: In this paper a hardware-software implementation of adaptive correlation filter tracking for a 3840 ⨯ 2160 @ 60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. Correlation filters gained popularity in recent years because of their efficiency and good results in the VOT (Visual Object Tracking) challenge. An implementation of the MOSSE (Minimum Output Sum of Squared Error) algorithm is presented. It utilizes 2-dimensional FFT for computing correlation and updates filter coefficients in every frame. The initial filter coefficients are computed on the ARM processor in the PS (Processing System), while all other operations are preformed in PL (Programmable Logic). The presented architecture was described with the use of Verilog hardware description language.

System-on-Chip Platform for Safety-Relevant Structural Health Monitoring Applications

Abstract: In domains such as aerospace, wind turbines and railway, structures are exposed to tough environmental conditions. Structural Health Monitoring (SHM) systems offer the possibility to realize condition-based maintenance (CBM) and monitoring methods in order to prevent fatal accidents. For this reason, real-time processing of the acquired data is necessary. The real-time processing of this data in combination with safety requirements and high availability needs a safe platform that can provide high computational power. In this paper a System-on-Chip (SoC) platform is shown, which addresses these challenges through the combination of an ARM processor with Programmable Logic (PL). Based on the SoC, the integration of safety-critical and non safety-critical functionality is possible in a single device. Targeting the standards EN 61508, EN 50126 and EN 50657 the introduction of SoCs as a platform for certifiable systems is discussed. With diversity and redundancy on a single chip, SoCs are ideally suited for requirements such as reliability, availability, maintainability and safety. Moreover, the implementation of functions in hardware on the PL in connection with the Programmable System (PS) facilitates real time data processing.