Showing papers in "Solid-state Electronics in 2019"

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Abstract: This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

The concept of electrostatic doping and related devices

Abstract: Electrostatic doping aims at replacing donor/acceptor dopant species with free electron/hole charges induced by the gates in ultrathin MOS structures. Highly doped N+/P+ terminals and virtual P-N junctions can be emulated in undoped layers prompting innovative reconfigurable devices with enriched functionality. The distinct merit is that the carrier concentration and polarity (i.e., electrostatic doping) are tunable via the gate bias. After presenting the fundamentals, we review the family of electrostatically-doped devices fabricated with emerging or mature technologies (nanowires, nanotubes, 2D materials, FD-SOI). The multiple facets of the Hocus Pocus diode are discussed by underlining the difference with classical physical diodes. Electrostatic doping gave rise to a number of band-modulation devices with outstanding memory and sharp-switching capability. The concept, intrinsic mechanisms and typical applications are described in detail.

Lightweight flexible indium-free oxide TFTs with AND logic function employing chitosan biopolymer as self-supporting layer

Abstract: Chitosan, a natural polysaccharide, is nontoxic, lightweight and biodegradable, which exhibits a great potential for the emerging flexible and “green” electronic applications. Here, lightweight flexible aluminum-zinc-oxide (AZO) thin-film transistors (TFTs) are fabricated using chitosan biopolymer as self-supporting layer. This kind of biopolymer electrolyte can provide a strong electric-double-layer effect, which leads to a large capacitance with lower energy consumption. With the low-cost indium-free AZO deposited onto the chitosan film as the coplanar gate and source/channel/drain electrodes, the transistor shows a moderate on/off ratio of ∼104, a relatively ideal field-effect mobility of 0.3 cm2/Vs and a moderate sub-threshold swing of 0.65 V/dec. Moreover, logic “AND” function is realized in the flexible device with two coplanar gates as the input terminals. Such chitosan-gated flexible TFT devices can provide promising candidates for the next generation wearable and “green” electronics.

Degradation and failure mechanism of AlGaN-based UVC-LEDs

Abstract: The degradation behaviors of flip-chip 260 nm ultraviolet light emitting diodes (UVC-LEDs) were studied using in-situ accelerated system and different analytical technologies. The optical power of LEDs stressed at a constant DC current of 20 mA decreased to ~63% of the initial value after 150 h of operation. The failure mechanisms were investigated systematically by using current-voltage measurements, Secondary Ion Mass Spectroscopy, Transient Thermal Analysis, Scan Electron Microscopy, etc. The results show that: the concentration of H in p-GaN layer decreased from 4.5e17 atoms/cm3 for the unstressed samples to 6.0e16 atoms/cm3 for stressed sample, while there is no change for the Mg concentration, indicating the hydrogen dissociated from the Mg-H complex resulting from the activation of the Mg-dopant during the initial period; the increase of the current for the reverse bias region and the low-forward bias region during stress is due to the increase of defect-assisted carrier tunneling; the electro-migration of contact metal may generate the current leakage channel, which degraded the optical power of the LEDs. These results will help to improve the reliability design of AlGaN-based deep-UV LEDs.

Gas sensing characteristics of the FET-type gas sensor having inkjet-printed WS2 sensing layer

Abstract: This paper investigates the gas sensing characteristics of the MOSFET-type sensor having an inkjet-printed WS2 sensing layer. The drain current of the gas sensor increases when NO2 gas is injected into the test chamber since NO2 gas is an oxidizing gas that extracts electrons from the sensing layer. On the contrary, the drain current decreases when H2S gas is injected into the test chamber since H2S gas is a reducing gas that donates electrons to the sensing layer. In both cases, the change of the drain current increases as the gas concentration increases. However, for other gases (NH3 and CO2), the gas sensor has a small change of the drain current. The responses of the gas sensor to 10 ppm NO2, H2S, NH3, and CO2 gases are 15.20%, 7.18%, 1.66%, and 3.02%, respectively. Therefore, the WS2 sensor has a high selectivity for NO2 gas among the four target gases.

Investigation on single pulse avalanche failure of SiC MOSFET and Si IGBT

Abstract: In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT. The experimental results show that SiC MOSFET can handle ∼20% higher avalanche energy at the same current density, and ∼50% higher current density at the same amount of energy. As SiC device has 5× smaller chip size, the advantage will disappear when comparison is performed with avalanche current. To improve the avalanche current capability of SiC MOSFET, failure mechanisms are analyzed. At first, the junction temperature is calculated with V-T model and thermal model, from which a linear dependence of temperature on avalanche current is revealed. Then, the probability of parasitic BJT turn-on is modeled analytically with the base-to-emitter resistance/voltage, which is found to be highly dependent on the p+ ohmic contact resistance (ρc) and base doping concentration (NB) designs of the device. Based on the modeling results, at the peak junction temperature 650 K in UIS test, the BJT turn-on can already be triggered for SiC MOSFET. The failure trigger temperature can be raised with a higher NB and lower ρc design, thus the avalanche current capability can be increased accordingly. On the other hand, with a much deeper p+ body structure design, the Si IGBT can prevent the BJT latch-up failure. Based on the failure analysis, a trench source structure of SiC MOSFET is proposed to further improve the avalanche capability for smaller chip size design.

SnO2 nanoparticles/TiO2 nanofibers heterostructures: In situ fabrication and enhanced gas sensing performance

Abstract: A facile electrospinning technique followed with calcinations in air has been accepted as a straight forward protocol for the research and development of SnO2/TiO2 heterostructures which are composed of SnO2 nanoparticles and TiO2 nanofibers. Characterizations of the nanocomposites by series of testing techniques indicate that the SnO2 nanoparticles were prepared and uniformly anchored on the surface of TiO2 nanofibers. Gas sensors were fabricated to investigate the gas-sensing behaviors of SnO2/TiO2 nanocomposites. Comparing with pure SnO2 nanoparticles and TiO2 nanofibers, SnO2/TiO2 nanocomposites exhibited better gas-sensing performance. The SnO2/TiO2 heterojunctional composites with the mass ratio of 1.5:1 presented an optimum operating temperature of 240 °C. The maximum gas response relative to 100 ppm ethanol is 9.58, which is about 1.89 and 1.88 times higher, respectively, than pure TiO2 nanofibers and SnO2 nanoparticles. Meanwhile, the gas sensors prepared with SnO2/TiO2 nanocomposites also had shorter response and recovery time and long term stability. The enhanced sensing properties could be ascribed to the formation of heterojunction and the synergetic effect of SnO2 and TiO2 together with its unique nanoparticle attached fibrous architectures.

A Sub-35 pW Axon-Hillock artificial neuron circuit

Abstract: Artificial Intelligence (AI) applications are developing at a high rate, facing soon a tremendous energy challenge. In this context, the original Axon-Hillock (AH) Artificial Neuron (AN) has been optimized to achieve ultra-low power (ULP) consumption. The membrane capacitance was taken out, and in order to drastically reduce its power consumption, the (feedback) capacitance is lowered to 5 fF, the transistors gate width is reduced to 120 nm and the supply voltage is decreased to as low as 200 mV. Designed and fabricated using 65 nm CMOS Technology, the refined AH neuron features a standby power of 11 pW, and when excited, a power consumption that does not exceed 30 pW for a firing frequency of 15.6 kHz. Its energy efficiency per spike is lower than 2 fJ / spike when the DC power is included (around 1 fJ / spike excluding the DC power), for an area of 31 µm2. These performance confer to this ULP AH neuron a high potential for future development of highly energy efficient Spiking Neural Networks, required to design future neuroprocessors embedded in various applications (smart visual sensors for autonomous vehicles, robotics).

Current-voltage analytical model and multiobjective optimization of design of a short channel gate-all-around-junctionless MOSFET

Abstract: In this paper we investigate the optimized design of a short channel gate-all-around-junctionless (GAAJ) metal-oxidesemiconductor field-effect-transistor (MOSFET), including the source-drain extensions, by means of genetic algorithm solutions applied to a compact current-voltage analytical model. In fact, due to the complex device structure, it seems useful to exploit a metaheuristic-based approach to search the optimal combination of the fundamental geometrical and physical parameters that lead to an improved performance. Through this analysis, different parameter constraints are imposed for the calculation of specific objective functions. In particular, for a fixed gate-drain bias level, the task pursues the maximization of the drain current and cut-off frequency while limiting the short channel (SC) effects. The MOSFET series resistance is also evaluated in the transition region of the Id – Vgs characteristics which appear, however, strongly affected by SC effects. The accuracy of the model is verified by comparison with experimental data reported in literature.

Lithography for now and the future

Abstract: Highlights Amount of transistors on chip oubles every 1.5–2 years accordig to Moore’s law. Multiple patterning is required to obtain ∼10–16 nm half-pitch using immersion lithography. EUV scanners will extend Moore’s Law for the foreseeable future. View of further extension of EUV in the future will be discussed in this article.

28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

Abstract: This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).

Wide band gap semiconductor technology: State-of-the-art

Abstract: Applications of the wide band gap (WBG) semiconductors, such as GaN, AlGaN, and InGaN, range from lighting and ultraviolet (UV) technology to high power, radiation hard, high temperature, terahertz (THz) and sub-THz electronics and pyroelectronics. Wurtzite (hexagonal) symmetry makes these materials to be quite different from conventional cubic semiconductors. Spontaneous and piezoelectric polarization associated with the wurtzite crystal structure induces two-dimensional electron gases at AlGaN/GaN, AlInN/GaN, and AlGaN/InGaN interfaces with sheet concentrations 10–20 times higher than those in Si CMOS. A high current carrying capability and a high breakdown field make these materials perfect for high power applications. Adjusting the energy gaps of AlxGa1−xN and of InxGa1−xN by varying the molar fraction changes the wavelength of light they emit or absorb and enables light and UV emitters, solar cells, and photodetectors operating from THz and infrared to deep UV range. Blue, green, and white LEDs using InGaN revolutionized smart solid-state lighting. AlGaN UV LEDs are used for water purification, fighting antibiotic resistant bacteria and viruses, and dramatically increasing produce storage time. InN, ZnO, and BN have potential to compete with the AlN/GaN family. Diamond has re-emerged not only as a substrate for a record heat removal but also as a viable THz detector material. The WBG technology has many difficult problems to solve. High dislocation density in the WBG materials leads to a low efficiency of deep AlGaN UV LEDs and reliability problems of high power devices. Non-uniformities of the electric field distribution cause a premature breakdown. Using ultrathin WBG quantum well layers and nanowires and exploring radically new physics-based device designs might alleviate or even solve these problems.

Nanowire reconfigurable FET as biosensor: Based on dielectric modulation approach

Abstract: In this paper, we have developed analytical surface potential and threshold voltage model of nanowire reconfigurable Field Effect Transistor (FET) which acts as a biosensor to detect the biomolecules, based on dielectric modulation approach. Due to its reconfigurable behavior, it acts as both p-type and n-type depending on the polarity of the biasing and hence find wide spread applications in the field of Programmable Logic Arrays (PLAs). The same is employed here as a bio sensor device with split gates and a cavity for biomolecules immobilization on a thin layer of silicon dioxide as adhesive layer. When the biosensor interacts with the bio targets of the cavity, the electrostatic properties of the device including variation in potential profile and threshold voltage shift get affected and thus have been identified as detection metric in this present work. The characteristic trends of the biosensor are studied with varying height, dielectric constant and charge of the bio-species as polarity of the applied biases change. In addition to this, sensitivity of nanowire RFET is analyzed by assessing the threshold voltage variation which is further compared with equivalent MOSFET biosensor. All the analytical results obtained are corroborated with technology computer-aided-design (TCAD) simulation data to verify the precision of our model.

Two-pulse sub-ns switching scheme for advanced spin-orbit torque MRAM

Abstract: The steady increase in performance and speed of modern integrated circuits is continuously supported by constant miniaturization of complementary metal-oxide semiconductor (CMOS) devices. However, a rapid growth of the dynamic and stand-by power due to transistor leakages becomes a pressing issue. A promising way to slow down this trend is to introduce non-volatility in circuits. The development of an electrically addressable non-volatile memory combining high speed and high endurance is essential to achieve these goals. To further reduce the energy consumption, it is essential to replace SRAM in modern hierarchical multi-level processor memory structures with a non-volatile memory technology. The spin-orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is thus suitable for applications in caches. However, its development is still hindered by relatively high switching currents and the need of an external magnetic field for deterministic switching of perpendicularly magnetized layers. The switching by means of two orthogonal current pulses allows achieving deterministic sub-500 ps and magnetic field-free switching in perpendicularly magnetized rectangular structures. Complementing the two-pulse switching scheme with weak perpendicular interface-induced magnetic anisotropy reduces the switching current significantly for achieving sub-500 ps switching in in-plane structures.

High-periphery GaN HEMT modeling up to 65 GHz and 200 °C

Abstract: In this article, we report on the temperature-dependent GaN HEMT behavior. To evaluate the potentialities of this kind of active solid-state electronic device at its best, the experiments are performed at extreme operating conditions. As a case study, we consider a large 0.25-μm GaN HEMT with a gate periphery of 1.5 mm, providing a high dissipated power of 5.1 W. The tested semiconductor device is characterized by measuring scattering parameters at high frequencies up to 65 GHz and at high ambient temperature up to 200 °C. To assess the impact of the thermal effects on high-frequency GaN HEMT performance, an equivalent circuit is analytically extracted and then used to determine the main RF figures of merit. The achieved experimental results show evidence that the increase of the temperature causes a significant degradation in device performance.

Epitaxy of Si-Ge-Sn-based heterostructures for CMOS-integratable light emitters

Abstract: The recent rise of GeSn-based optically pumped lasers have multiplied the efforts to fabricate a fully CMOS compatible and group IV-based light emitter. Their integration with Si-based electronics may yield heavily reduced power consumption in integrated circuits and pave the way towards new sensing or medical applications. Here, we discuss the epitaxy of group IV GeSn and SiGeSn semiconductors and show their suitability for light emitting applications. Double and multi quantum well heterostructures are evaluated, whereby the latter enables an inherently easier control over the formation of deleterious misfit defects. Consequently, microdisk lasers fabricated from those show greatly enhanced light emission and reduced lasing thresholds. The use of in-situ p-i-n doping schemes allow the formation of light emitting diodes, resulting in electrically-enabled light emission already at room temperature.

Analysis of resistive switching processes in TiN/Ti/HfO2/W devices to mimic electronic synapses in neuromorphic circuits

Abstract: The potential of resistive switching (RS) devices based on TiN/Ti/HfO2/W stacks to mimic synapses within a neuromorphic applications context is analyzed in depth. The fabrication and characterization process are explained and a physically-based modeling description is performed to understand the devices resistive switching operation and conductance modulation. The model employed considers truncated-cone shaped conductive filament (CF) geometries and parasitic ohmic resistances linked to the device conductive filaments in addition to device capacitances. The temporal evolution is analysed assuming a valence change memory operation, where the oxide surrounding the CF is considered as well as the CF thermal description. A complete series of RS cycles has been fitted with the model by means of the gradient descent algorithm to study the compliance current effects on the conductance modulation. To do so, experimental and modeled results are extensively compared.

NanoElectronics Roadmap for Europe: From Nanodevices and Innovative Materials to System Integration

Abstract: The NEREID project ("NanoElectronics Roadmap for Europe Identification and Dissemination") is dedicated to mapping the future of European Nanoelectronics. NEREID's objective is to develop a medium and long term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European eco-system. The roadmap will also identify promising novel nanoelectronic technologies, based on the advanced concepts developed by Research Centres and Universities, as well as identification of potential bottlenecks along the innovation (value) chain. Industry applications include Energy, Automotive, Medical/Life Science, Security, loT, Mobile Convergence and Digital Manufacturing. The NEREID roadmap covers Advanced Logic and Connectivity, Functional Diversification (Smart Sensors, Smart Energy and Energy for Autonomous Systems), Beyond-CMOS, Heterogeneous Integration and System Design as well as Equipment, Materials and Manufacturing Science. This article gives an overview of the roadmap's structure and content.

Efficient bimetallic nanoparticles embedded-porous silicon CO gas sensor

Abstract: In this study, the surface modification process involving the embedding of Au or Pd monometallic and Au Pd bimetallic alloy nanoparticles within porous silicon-based gas sensor was investigated. Porous silicon layer (P-si) was prepared by photo electrochemical etching (PECE) by using 635 nm diode laser of 25 mW/cm2 intensity. AuNPs/P-si, PdNPs/P-si and Au PdNPs/P-si hetero structures were prepared by ion reduction process. This was materialized dipping fresh P-si in a salt solution containing HAuCl4 and PdCl2; mixed at ratio 1:1 for about (1.2, 5 and 2 min), respectively. The heterostructures were investigated by utilizing scanning electron microscopy (SEM), FTIR analysis, X-ray diffraction (XRD) and energy dispersive X-ray analysis (EDS). Efficient gas sensing process was recorded for modified porous silicon (P-si) gas sensor with smallest bimetallic Au Pd nanoparticles size. Considerable improvements were noticed in sensitivity and temporal response after incorporating the bimetallic Au Pd nanoparticles into the silicon matrix as compared to bare P-si and monometallic nanoparticles gas sensors due to the high specific surface area and the higher value of the barrier height of Au PdNPs/P-si hetero structures.

Exploiting topological matter for Majorana physics and devices

Abstract: Quantum computing promises to solve problems, which are impossible for classical computers. Among the different schemes of how to design a quantum computer, one particularly exotic version has raised a lot of attention lately. Although so-called topological quantum computing is a rather young concept, it promises to reduce the required overhead of physical quantum bits per logical quantum bit by a factor of 100–1000, due to an intrinsic protection against certain quantum errors. Once the fundamental mechanism – braiding of Majorana zero modes – is demonstrated, the topological scheme could become the most promising in terms of scalability. This article offers a short introduction to the topological concept and also aims to review the latest developments and efforts in this rapidly evolving field. In addition to this, it discusses different platforms for experimental realization of topologically protected devices. One particularly promising platform might evolve when in-situ fabrication techniques are applied to magnetically doped topological insulators. As a result, it should become possible to fabricate high fidelity Majorana devices for quantum computational tasks in a scalable fashion.

High mobility solution processed MoS2 thin film transistors

Abstract: A simple wet-chemical synthesis of layered MoS2 thin films on sapphire is reported. The gap in understanding solution processed MoS2 deposition needs to be closed to exploit all its excellent properties for low-cost applications. In this work, as deposited Mo-precursor thin films were prepared based on the solubility and coating properties of Molybdenum(V) chloride in 1-Methoxy-2-propanol. Subsequent annealing of the deposited amorphous Mo-precursor films in the presence of sulfur resulted in the formation of highly crystalline layered MoS2 films on sapphire. Improved crystallinity of the deposited films was achieved by increasing the process temperature and performing the post-annealing treatment. Post-annealing at temperatures above 900 °C increased the uniformity of multilayer films, together with the increase of MoS2 grain size. For charge transport analysis, top-gate top-contact thin film transistors (TFTs) based on these solution processed MoS2 films were fabricated. Ionic liquid gating of the TFT devices exhibited n-type semiconducting behaviour with field-effect mobility as high as 12.07 cm2/Vs and Ion/off ratio ∼ 106. X-ray photoelectron spectroscopy measurements revealed that the films annealed between 900 °C and 980 °C had an average chemical composition of S/Mo ∼ 1.84. This facile liquid phase synthesis method with centimeter-scale uniformity and controllable film thickness up to 1.2 ± 0.65 nm is suitable for low-cost preparation of other transition metal dichalcogenides thin films in next-generation electronics.

Effect of degree of strain relaxation on polarization charges of GaN/InGaN/GaN hexagonal and triangular nanowire solar cells

Abstract: The innovative contribution of this paper is to derive polarization charges in hexagonal and triangular GaN/InGaN/GaN core/shell/shell nanowire solar cells considering effect of degree of strain relaxation (R) and appropriate stiffness coefficients. The crystal orientation angle, φ and non-linear effect of spontaneous polarization are tailored with strain calculations for a better precision of polarization charges in nanowire type devices. The article also formulated the effect of polarization charges while InGaN layers are grown above or below GaN layer in both types of nanowires depending on the lattice expansion or compression. The model accounts an innovative concept of polarization charges distribution with respect to growth of crystal orientation and strain relaxation. It is observed that nanowire solar cell with triangular geometry could be good enough for efficient generation of power as compared to hexagonal nanowire solar cell. This concept of one triangular nanowire solar cell exhibits an efficiency of 3.18% with 90.34% fill factor under 1 Sun AM1.5 illumination with 20% ‘In’ composition.

Ohmic contact to AlGaN/GaN HEMT with electrodes in contact with heterostructure interface

Abstract: In order to alleviate the negative impacts of high temperature (850 °C) annealing on high electron mobility transistor (HEMT) technology, a process required only low temperature annealing (less than 600 °C) was introduced to form ohmic contact to HEMT. By the process, the electrode was in contact with the AlGaN/GaN interface. The value of specific contact resistivity (ρc) of the ohmic contact was 6.29 × 10−5 Ω cm2. An improved HEMT power device was presented. For comparison, a conventional device with Ti/Al/Ni/Au ohmic contact annealed at 850 °C was prepared. It was found that after annealing at 600 °C, the sheet resistance (Rsh) of the improved device decreased to 313 Ω/□ (74.5% of that of the conventional device), and the advantage of our process on device performance was greater as the distance between ohmic contacts increased. The saturation current of the improved device was increased by approximately 23% when the distance between source and drain was 40 μm.

New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures

Abstract: We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (Lrt) yields a very steep slope and higher ION compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (1021 cm−3) thin layer at the bottom for extremely small body thickness (TSi

Improved efficiency of organic light emitting devices using graphene oxide with optimized thickness as hole injection layer

Abstract: Organic Light-Emitting Diodes (OLEDs) with graphene oxide (GO) as hole injection layer (HIL) have been demonstrated. The OLED devices possess structures of ITO/GO(x nm)/NPB(40 nm)/Alq3(70 nm)/LiF(0.5 nm)/Al(100 nm), it is found that as the thickness of GO-HIL is a 3.6 nm an optimal current efficiency of 4.4 cd/A and a brightness of 15,770 cd/m2 were achieved, respectively, which are higher than that of reference device without GO-HIL layer (1 cd/A and 4735 cd/m2). We reason that the improvement of electroluminescent (EL) intensity would be ascribed to the smoothed ITO surface and the reduced hole-injection barrier due to the high work function of GO layer. In terms of the impendence spectroscopy analysis of hole-only devices (HODs), for electrical character of device is mainly depends on the bulk resistance of the HODs. As a result, the optimized EL device offers fallen bulk resistances, finally, the improvement in EL performance was obviously realized.

Influence of BEOL process on poly-Si grain boundary traps passivation in 3D NAND flash memory

Abstract: In this work, the influence of BEOL process on poly-Si grain boundary traps passivation in 3D NAND flash is investigated. Two hydrogenation methods in final passivation process are compared and hydrogen in passivation layer is found to be more effective for poly-Si grain boundary traps (GBT) passivation, according to device characteristics. Interlayer used as copper cap layer can also act as potential hydrogen diffusion source as well as final passivation layer. Besides, different interlayer films in BEOL process are found to be critical to cell device characteristics. It is considered that BEOL film stacks can influence poly-Si GBT density and cell device characteristics during subsequent hydrogen passivation process.

Improved performance of fully-recessed normally-off LPCVD SiN/GaN MISFET using N2O plasma pretreatment

Abstract: An effective and simple approach for gate-recessed normally-off GaN-based MISFETs is proposed to suppress the high temperature induced degradation during low pressure chemical vapour deposition (LPCVD) in gate-recessed normally off GaN-based MISFET. After a N2O plasma treatment on GaN channel prior to LPCVD SiN, the LPCVD SiN/GaN MISFET exhibits a maximum drain current of 607 mA/mm, 3 times higher than that without N2O plasma pretreatment, a threshold voltage of +1.2 V at ID = 0.1 mA/mm, off-state hard-breakdown voltage of 1348 V with LGD = 20 μm, and gate leakage current below 15 nA/mm in the whole gate swing to +20 V. The interface states characterization in MISFETs show that about 3 times lower interface trap density was achieved in MISFET with N2O plasma pretreatment compared to that in SiNx/GaN transistor without such surface treatment.

Feasibility of plasmonic circuits for on-chip interconnects

Abstract: Feasibility of fabricating plasmonic circuits by complementary metal–oxidesemiconductor (CMOS) compatible processes is presented, and the circuit performances are numerically and experimentally discussed from the viewpoint of operating speed and energy loss. The transmission speed of plasmonic signals, which is governed by the dispersion of circuits, is calculated to be about two orders of magnitude higher than that of electric signals. The energy loss per single transmitted-bit is estimated using shot-noise limits, and it is clarified that plasmonic signals are superior to electric ones if the transmitted distance is set to an area within a few hundred micrometers. Based on these results and the experimental results of each plasmonic components, the feasibility of plasmonic circuits are demonstrated. In addition, the feasibility of the functional expansion of plasmonic circuits, such as wavelength-division-multiplexing networks, is discussed using experimental values of plasmonic components fabricated by CMOS-compatible processes. These plasmonic circuits and networks can be merged into silicon integrated circuits on a silicon substrate using CMOS compatible processes.

On the extraction of resistivity and area of nanoscale interconnect lines by temperature-dependent resistance measurements

Abstract: Several issues concerning the applicability of the temperature coefficient of the resistivity (TCR) method to scaled interconnect lines are discussed. The central approximation of the TCR method, i.e. the substitution of the interconnect wire TCR by the bulk TCR becomes doubtful when the resistivity of the conductor metal is strongly increased by finite size effects. Semiclassical calculations for thin films show that the TCR deviates from bulk values when the surface roughness scattering contribution to the total resistivity becomes significant with respect to grain boundary scattering, an effect that might become even more important in nanowires due to their larger surface-to-volume ration. In addition, the TCR method is redeveloped to account for line width roughness. It is shown that for rough wires, the TCR method yields the harmonic average of the cross-sectional area as well as, to first order, the accurate value of the resistivity at the extracted area. Finally, the effect of a conductive barrier or liner layer on the TCR method is discussed. It is shown that the liner or barrier parallel conductance can only be neglected when it is lower than about 5–10% of the total conductance. It is furthermore shown that neglecting the liner/barrier parallel conductance leads mainly to an overestimation of the cross-sectional area of the center conductor whereas its resistivity is less affected.

The influence of grain boundary interface traps on electrical characteristics of top select gate transistor in 3D NAND flash memory

Abstract: The electrical characteristics of top select gate transistor (TSG) has been investigated in vertical channel three dimensional NAND flash memory. TSG shows wider initial Vth distribution as compared with memory cells, and even worse after erase. By experimental analysis and TCAD simulation, a physical model based on grain boundary (GB) interface traps is proposed to explain the mechanism. Grain boundary traps in offset region between bit line contact and TSG can induce a higher local potential barrier in channel, which results in higher TSG initial Vth. Besides, random GB position within offset region, leads to worse variation of TSG initial Vth. Furthermore, the local potential barrier in offset region of TSG cannot be reduced by erase operation, leading to worse Vth distribution after erase. According to proposed model, two methods with optimization of offset doping energy and poly-Si GB trap passivation condition are proposed to achieve tight distribution and improved erase uniformity.