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Showing papers on "Relaxation oscillator published in 2023"


Journal ArticleDOI
01 Jan 2023
TL;DR: In this article , the analytical and numerical investigations of the fractal resistive-capacitive-inductive shunted Josephson junction (FRCLSJJ) and its microcontroller implementation (MCI) are described.
Abstract: The paper captures the analytical and numerical investigations of the fractal resistive–capacitive–inductive shunted Josephson junction (FRCLSJJ) and its microcontroller implementation (MCI). The rate equations of FRCLSJJ are established and based on the Routh–Hurwitz criterion, two equilibrium points are reported with one unconditionally stable and the other unstable for the direct current used for junction excitation less than or equal to one. When this current is greater than one, the FRCLSJJ exhibits no equilibrium point. The contribution of fractal parameters to the dynamics of FRCLSJJ is investigated on fast bursting, regular spiking, relaxation behaviors, and periodic bursting. The FRCLSJJ is characterized by fine dynamics such as different presentations of complex behaviors, the coexistence of periodic and chaotic hidden attractors, chaotic hidden attractors, antimonotonicity, periodic attractors, and periodic and chaotic bubble hidden attractors for varying system parameters. And in the last section of the investigation, the MCI of FRCSJJ is realized with the results establishing a qualitative agreement with numerically simulated results.

2 citations


Journal ArticleDOI
TL;DR: In this article , a fully integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented, which includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators.
Abstract: A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator’ output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works.

2 citations


Journal ArticleDOI
TL;DR: In this article , the authors applied qualitative analysis to an existing model of a gene regulatory network in which a protein dimer inhibits its own transcription and upregulates its own translation rate.

1 citations


Journal ArticleDOI
TL;DR: In this article , the authors consider a double phosphorylation cycle, a ubiquitous signaling component, having the ability to display bistability, a behavior strongly related to the existence of positive feedback loops, and show that the two feedbacks together ensure two types of oscillations, the relaxation-type ones and a smoother type of oscillation functioning in a very narrow range of frequencies, in such a way that outside that range, the amplitude of the oscillations is severely compromised.
Abstract: Abstract In this article, we consider a double phosphorylation cycle, a ubiquitous signaling component, having the ability to display bistability, a behavior strongly related to the existence of positive feedback loops. If this component is connected to other signaling elements, it very likely undergoes some sort of protein–protein interaction. In several cases, these interactions result in a non-explicit negative feedback effect, leading to interlinked positive and negative feedbacks. This combination was studied in the literature as a way to generate relaxation-type oscillations. Here, we show that the two feedbacks together ensure two types of oscillations, the relaxation-type ones and a smoother type of oscillations functioning in a very narrow range of frequencies, in such a way that outside that range, the amplitude of the oscillations is severely compromised. Even more, we show that the two feedbacks are essential for both oscillatory types to emerge, and it is their hierarchy what determines the type of oscillation at work. We used bifurcation analyses and amplitude vs. frequency curves to characterize and classify the oscillations. We also applied the same ideas to another simple model, with the goal of generalizing what we learned from signaling models. The results obtained display the wealth of oscillatory dynamics that exists in a system with a bistable module nested within a negative feedback loop, showing how to transition between different types of oscillations and other dynamical behaviors such as excitability. Our work provides a framework for the study of other oscillatory systems based on bistable modules, from simple two-component models to more complex examples like the MAPK cascade and experimental cases like cell cycle oscillators.

1 citations


Journal ArticleDOI
TL;DR: In this article , a complete smart capacitive sensor solution based on a microcontroller was developed, which includes the development of both the hardware and software, including an 8-bit microcontroller equipped with two timers/counters and a three-gate stable RC relaxation oscillator.
Abstract: A complete smart capacitive sensor solution based on a microcontroller was developed. This approach includes the development of both the hardware and software. The hardware part comprises an 8-bit microcontroller equipped with two timers/counters and a three-gate stable RC relaxation oscillator. The software part handles system configuration, measurement control, communication control, and data processing. Hence, the microcontroller acts as a frequency meter with an adaptive measuring time, and the relaxation oscillator generates a square wave with a frequency depending on the value of the capacitance of the sensor. The paper also proposes a calibration method that reduces the measurement range to 1 pF. The experimentally proven relative measurement errors of sensor capacitance are less than 0.012% for values smaller than 12 pF, and less than 0.0084% for values from 12 pF to 300 pF.

Journal ArticleDOI
TL;DR: In this article , a temperature compensation technique with variable threshold control for Voltage Controlled Relaxation Oscillator (VCRO) is presented, where the voltage to current conversion circuit reduces the drift in the frequency gain across temperature by introducing a PMOS-NMOS current gain compensation scheme.
Abstract: Relaxation oscillators with wide dynamic range are required for low power frequency modulated switch mode DCDC regulator designs. In this brief, a temperature compensation technique with variable threshold control for Voltage Controlled Relaxation Oscillator (VCRO) is presented. The voltage to current conversion circuit reduces the drift in the frequency gain across temperature by introducing a PMOS-NMOS current gain compensation scheme. The current gain circuit also allows absolute control on the minimum value of control voltage after which VCRO starts doing voltage to frequency conversion. This restricts the amplifier to go out of saturation which is inherently generating the control voltage for VCRO. Measurement results show that across temperature range of -40 oC to 150 oC, the oscillator achieves a temperature stability of 187 ppm/oC at 18MHz and 171 ppm/oC at 92.5MHz respectively. Implemented in 90nm process node, it occupies 57μm×32μm area while dissipating 2.61 nW/KHz from a 1.5V supply.

Journal ArticleDOI
TL;DR: In this paper , a 2.15 µW/MHz relaxation oscillator with a dynamic range of frequency from 47.5 MHz to 80 MHz was proposed to reduce the power consumption and improve energy efficiency.
Abstract: This paper presents a 2.15 µW/MHz at the frequency of 64 MHz relaxation oscillator with a dynamic range of frequency from 47.5 MHz to 80 MHz. To reduce the power consumption and improve energy efficiency, this work employs only one comparator and one capacitor to generate the output clock in comparison with conventional relaxation oscillator structures. A total of 50% ± 5% of the duty cycle is obtained for the output clock by implementing an auxiliary comparator. The proposed relaxation oscillator uses the output voltages of an external low-dropout (LDO) voltage and bandgap reference (BGR) for the required supply and reference voltages, respectively. Two current sources are implemented to provide the required currents for trimming the output frequency and driving the comparators. Measurement results indicate that the relaxation oscillator achieves a temperature coefficient (TC) of 130 ppm/°C over a wide temperature range from −25 °C to 135 °C at the frequency of 64 MHz. The relaxation oscillator consumes 115 µA of current at the frequency of 64 MHz under a low-dropout (LDO) voltage of 1.2 V. The proposed relaxation oscillator is analyzed and fabricated in standard 90 nm complementary metal-oxide semiconductor (CMOS) process, and the die area is 130 µm × 90 µm.


Journal ArticleDOI
29 May 2023-Sensors
TL;DR: In this article , a temperature sensor based on temperature-frequency conversion using 180 nm CMOS technology is proposed, which consists of a proportional-to-absolute temperature (PTAT) current generating circuit, a relaxation oscillator with oscillation frequency proportional to temperature (OSC-PTAT), and a relaxation OSC-CON, and a divider circuit cascaded with D flip-flops.
Abstract: This paper proposes a temperature sensor based on temperature-frequency conversion using 180 nm CMOS technology. The temperature sensor consists of a proportional-to-absolute temperature (PTAT) current generating circuit, a relaxation oscillator with oscillation frequency proportional to temperature (OSC-PTAT), a relaxation oscillator with oscillation frequency independent of temperature (OSC-CON), and a divider circuit cascaded with D flip-flops. Using BJT as the temperature sensing module, the sensor has the advantages of high accuracy and high resolution. An oscillator that uses PTAT current to charge and discharge capacitors to achieve oscillation, and utilizes voltage average feedback (VAF) to enhance the frequency stability of the oscillator is tested. Through the dual temperature sensing process with the same structure, the influence of variables such as power supply voltage, device, and process deviation can be reduced to a certain extent. The temperature sensor in this paper was implemented and tested with a temperature measurement range of 0–100 °C, an inaccuracy of +0.65 °C/−0.49 °C after two-point calibration, a resolution of 0.003 °C, a resolution Figure of Merit (FOM) of 6.7 pJ/K2, an area of 0.059 mm2, and a power consumption of 32.9 μW.

Posted ContentDOI
30 Jun 2023
TL;DR: In this paper , the authors show that the mechanism behind the avalanches is based on an inhibitory effect of interactions, which may quench the spiking of units due to an interplay with the maximal canard.
Abstract: The activity in the brain cortex remarkably shows a simultaneous presence of robust collective oscillations and neuronal avalanches, where intermittent bursts of pseudo-synchronous spiking are interspersed with long periods of quiescence. The mechanisms allowing for such a coexistence are still a matter of an intensive debate. Here, we demonstrate that avalanche activity patterns can emerge in a rather simple model of an array of diffusively coupled neural oscillators with multiple timescale local dynamics in vicinity of a canard transition. The avalanches coexist with the fully synchronous state where the units perform relaxation oscillations. We show that the mechanism behind the avalanches is based on an inhibitory effect of interactions, which may quench the spiking of units due to an interplay with the maximal canard. The avalanche activity bears certain heralds of criticality, including scale-invariant distributions of event sizes. Furthermore, the system shows an increased sensitivity to perturbations, manifested as critical slowing down and a reduced resilience.

Proceedings ArticleDOI
18 Jun 2023
TL;DR: In this paper , a dynamically biased, high-speed comparator architecture was proposed to achieve low quiescent power consumption by temporarily providing a large amount of dynamic current near to the comparison point when both inputs are getting close to each other.
Abstract: This paper presents a dynamically biased, high-speed comparator architecture consuming a very low quiescent power. In conventional comparator topology, there is an underlying trade-off between the speed and the quiescent power consumption. The proposed comparator adopts a dynamic current boosting mechanism that momentarily provides a large amount of dynamic current near to the comparison point when both inputs of the comparator are getting close to each other. However, when those input voltages are widely separated, the proposed comparator enters to a low current state where the excess dynamic current has been reduced to minimize the quiescent power. To appreciate its benefits, a relaxation oscillator has been developed using the proposed comparator, targeting a nominal frequency of 1 MHz in 180 nm CMOS process. The simulation result shows that the quiescent power consumption of the proposed comparator has been decreased by ~6X as compared to the conventional fixed biased comparator while maintaining the same speed of operation. The quiescent power consumption of the relaxation oscillator has been decreased by >11X using the proposed comparator compared to the conventional one. This proves the effectiveness of the proposed technique.

Journal ArticleDOI
TL;DR: In this paper , the authors discuss some oscillators that generate sinusoidal, as well as other periodic signals, including the phase shift, Wien bridge, twin T, Colpittz and Hartley.
Abstract: Below, we discuss some oscillators that generate sinusoidal, as well as other periodic signals. The main principle of oscillating circuits is the use a voltage amplifier with positive feedback. This makes the circuit unstable and constantly oscillating. In signal generators there must also be present an element that defines the frequency. In high frequency oscillators this is an LC circuit. If we want to generate low frequency signals, the inductances may be impractical, for their physical size. So, in low frequency oscillators rather RC circuits are used. The typical oscillators, like the phase-shift, Wien bridge, twin T, Colpittz and Hartley are described. Other, non-sinusoidal oscillators are considered, including the relaxation oscillator, multi-vibrator and others.

Proceedings ArticleDOI
28 Apr 2023
TL;DR: In this article , a chip oscillator circuit for IoT equipment is presented, which can effectively reduce the impact of power supply voltage on frequency stability, improve stability and reduce area and power consumption without additional voltage.
Abstract: The research direction of this paper is a chip oscillator circuit for IoT equipment. This circuit can effectively reduce the impact of power supply voltage on frequency stability, improve stability and reduce area and power consumption without additional voltage. Moreover, this Relaxation oscillator is 0.18 μ Designed in the BCD process. The power supply voltage range is from 2.7V to 5V. The simulation results show that the maximum frequency change relative to the power supply voltage is 0.65%. It has excellent performance.

Journal ArticleDOI
TL;DR: In this paper , an out-of-plane capacitive accelerometer with low cross-axis sensitivity at high accelerations based on a CMOS MEMS process is developed, where a truss frame is designed to suspend the proof mass of the accelerometer.

Journal ArticleDOI
TL;DR: In this article , a dual cross correlation analog-front-end (DCC-AFE) circuit for a mutual capacitive panel is proposed to solve the problem of reduced recognition ability owing to the phase difference variation between the transmitted and received signals for a large load panel.
Abstract: This article presents a dual cross correlation analog-front-end (DCC-AFE) circuit for a mutual capacitive panel. The DCC-AFE circuit solves the problem of reduced recognition ability owing to the phase difference variation between the transmitted and received signals for a large load panel. A sparse collection algorithm is adopted to reduce the number of analog-to-digital converter (ADC) collections and microcontroller unit (MCU) operations in the proposed touch system. Only a 12-bit successive-approximation-register voltage-controlled-oscillator (SAR-VCO) ADC could meet the requirement. Based on this algorithm, both the power consumption and die area of the proposed analog-front-end (AFE) are significantly reduced. Moreover, we propose a calibration algorithm to improve the accuracy of the ADC. The proposed state-of-art touch integrated circuit (IC) was fabricated via a 110 nm CMOS process. The proposed AFE achieves 46.1 and 50.2 dB signal-to-noise ratio (SNR) with 384 and 128 Hz frame rates, respectively. The active area of the 64-channel AFE with ADC on the chip is 0.988 mm $^{2}$ , which only occupies a small area. The touch IC has an energy consumption of 3.58 nJ/node.


Journal ArticleDOI
TL;DR: In this paper , a model for analyzing dynamic large-signal characteristics of double-barrier resonant-tunneling diodes (RTDs) is presented based on the analysis of dynamical trajectories in phase space, defined by the RTD bias and electron density.
Abstract: A model for analyzing dynamic large-signal characteristics of double-barrier resonant-tunneling diodes (RTDs) is presented. The model is based on the analysis of dynamical trajectories in phase space, defined by the RTD bias and electron density in the RTD quantum well. We show that an accurate dynamic model can be reformulated in an approximate way, relying only on a directly measurable DC I–V curve and on few other RTD parameters, which could be easily estimated with simple DC calculations. We further demonstrate that a simple equivalent circuit, composed of a capacitor, inductor, and two resistors (RLRC), accurately describes the large-signal admittance of RTDs. The circuit elements can be described in terms of relaxation time, geometrical RTD capacitance, and low- and high-frequency resistors. The circuit has the very same structure as that previously derived for small-signal RTD admittance, although with deviating parameters, which are now dependent on the AC-signal amplitude. We show that the large-signal RTD relaxation time can be shorter and longer than the small-signal one. In the context of RTD oscillators, a shorter RTD relaxation time allows one to get higher output power at high frequencies. The availability of an accurate, general, but rather simple, physics-based model for analyzing large-signal RTD dynamics removes one of the major hindrances to the further development of sub-THz and THz RTD oscillators.

Book ChapterDOI
01 Jan 2023
TL;DR: In this article , an efficient inductance-to-time converter (LTC) is proposed to provide a quasi-digital output whose pulse-on-time is proportional to the inductance of a single-element type sensor.
Abstract: This paper presents an efficient Inductance-to-Time Converter (LTC) that provides a quasi-digital output whose pulse-on time is proportional to the inductance of a single-element type sensor. The LTC operates with a negative feedback mechanism, which ensures that the final output is independent of the linearity error present in the forward path elements of the converter. The proposed relaxation oscillator-based operation can enhance the update rate of the inductance measurement. In addition, the inductance measured using the converter is made insensitive to the series coil-resistance of the sensor. A prototype of the LTC with an update rate of 10 kHz was developed in the laboratory, with an excellent linearity performance along with a reduced settling time. It was observed that the design produced a worst-case linearity error of 0.29% and a settling time of 12.4 ms when the inductance was varied from 0 to 20 mH. Furthermore, the prototype showed negligible sensitivity towards the coil resistance of the sensor, with a worst-case error of 0.65%, when the series resistance was varied from 40 Ω to 1040 Ω. The test results indicate superior performance of the developed prototype over existing architectures.

Journal ArticleDOI
TL;DR: In this article , a robust relaxation-oscillator-based conditioning circuit for remotely located resistive sensors is proposed, which uses a simple analog architecture comprising an integrator, Schmitt trigger, inverter, and novel switching logic as its core blocks.
Abstract: A robust relaxation-oscillator-based conditioning circuit for remotely located resistive sensors is proposed in this article. The proposed circuit uses a simple analog architecture comprising an integrator, Schmitt trigger, inverter, and novel switching logic as its core blocks. The circuit provides a linear digital indication of the sensor resistance. The output of the proposed circuit is independent of many non-idealities such as bias-current and offset voltage of Op-amps, connecting lead and switch on-resistances, and mismatch/drift in the circuit components and power-supply levels. The proposed circuit has the capability to render all these merits while interfacing with various types of resistive sensor configurations. The working mechanism and analysis of the proposed circuit are described first in this article. The performance of the circuit is verified using simulation and experimental studies. Later, the immunity of the developed circuit from the effect of various parameters is also experimentally verified. Results show that the proposed circuit possesses a linear digital output and generates a low error in the output. The maximum nonlinearity is merely 0.07 % when a typical single-element-based sensor is interfaced with the developed circuit. The performance features of the developed circuit are also compared with the prior art and are observed to be adequate for interfacing industrial resistive sensors.

Journal ArticleDOI
TL;DR: In this article , the effects of different modulation modes of low frequency amplitude-modulated excitation on relaxation oscillations were investigated and a three-dimensional visualization was proposed to explore the relaxation oscillation induced by different modalities, providing insights into the system's dynamic behaviors from multiple perspectives.
Abstract: Low frequency amplitude-modulated excitation is a recently reported excitation that can induce relaxation oscillations and prolongs the system’s slow processes. This investigation aims to research the effects of different modulation modes of low frequency amplitude-modulated excitation on relaxation oscillations. Generally, intriguing dynamical characteristics can be observed in compound relaxation oscillations when amplitude-modulated modulation is introduced. Specifically, the quasi-static processes of the system exhibit different relaxation oscillations while the active phase of the relaxation oscillations remains relatively constant. We investigate the dynamical behaviors of the entire excitation through the fast-slow analysis method. For this purpose, a three-dimensional visualization is proposed to explore the relaxation oscillations induced by different modulation modes, providing insights into the system’s dynamical behaviors from multiple perspectives. The results show that the oscillations depend on the modulation mode of the amplitude-modulated excitation. Modulation frequency changes extend the quasi-static processes and increase the number of oscillations. Besides, variations in the modulation index can trigger amplitude variations that lead to an increased number of bifurcation points during overmodulation. Based on these findings, we reveal the dynamic mechanism of composite relaxation oscillations. Our study demonstrates that the introduction of amplitude-modulated excitation can induce compound relaxation oscillations in the system, and different modulation modes significantly influence the fast-slow dynamics. Moreover, our results provide a valuable reference for investigating other dynamic systems that incorporate amplitude-modulated excitation.

Posted ContentDOI
27 Feb 2023
TL;DR: In this paper , a model based on relaxation oscillation was proposed to generate a pair of symmetric clock signals for two-module regulation and loop termination. But the model is not suitable for loop control of molecular computations.
Abstract: Embedding efficient calculation instructions into biochemical system has always been a research focus in synthetic biology. One of the key problems is how to sequence the chemical reaction modules that act as units of computation and make them alternate spontaneously. Our work takes the design of chemical clock signals as a solution and presents a $4$-dimensional chemical oscillator model based on relaxation oscillation to generate a pair of symmetric clock signals for two-module regulation. We give detailed dynamical analysis of the model and discuss how to control the period and occurrence order of clock signals. We also demonstrate the loop control of molecular computations and provide termination strategy for them. We can expect that our design for module regulation and loop termination will help advance the embedding of more complicate calculations into biochemical environments.

Proceedings ArticleDOI
24 Jan 2023
TL;DR: In this paper , the authors proposed a novel ultra-low power time-domain temperature sensor, which consists of two current generators including one constant-with-temperature (CWT) current reference generator, relaxation oscillator, separation circuit and digital circuit system.
Abstract: This paper proposed a novel ultra-low power time-domain temperature sensor. It consists of two current generators including one constant-with-temperature (CWT) current reference generator, relaxation oscillator, separation circuit and digital circuit system. Both of current generators are used to drive the oscillator to produce a signal whose high level duration is complementary to absolute temperature, and low level duration is temperature-independent. The separation circuit is used to separate the high level duration and low level duration. The digital circuit system can quantify the separation circuit output and make a subtraction, and therefore obtain digitized temperature information. The temperature sensor is designed using a standard 0.18μm CMOS process. The simulation results show that it can measure temperature from 0°C to 60°C The power consumption of the complete system is 86.79 nW at 25°C The maximum conversion speed is 52 Sa/s under 1V voltage supply.