Showing papers on "Split-radix FFT algorithm published in 2006"

An efficient locally pipelined FFT processor

Abstract: The fast Fourier transform (FFT) is a very important algorithm in digital signal processing. The locally pipelined (LPPL) architecture is an efficient structure for FFT processor designing in a real-time embedded system. Two basic building blocks, to the LPPL FFT processor, the butterfly in pipeline, and address generating, are discussed in this brief. Based on the "deep" feedback to butterfly-2, a novel approach for pipelined architecture, the radix-2 single-path deep delay feedback architecture is proposed. For length-N discrete Fourier transform computation, the dominant hardware requirements are minimal for complex multipliers log/sub 4/N-1 and adders 2log/sub 4/N. As an integral need of the LPPL FFT processor design, address generating and coefficient store-load structures are also presented.

FFT Algorithm with High Accuracy for Harmonic Analysis in Power System

Abstract: The Fast Fourier Transform(FFT) cannot be directly used to the harmonic analysis of electric power system because of its higher error,especially the phase error when used with a sample sequence which is not synchronized with the signal.To reduce the influence of an unsynchronized sample sequence on FFT and to improve the precision of harmonics in electric power system,this paper improves the algorithm by using windows and interpolation methods.The paper firstly addressed the leakage and picket fence effects of FFT briefly and then analyzes the interpolation algorithm on Rife Vincent(I) window in detail.Besides,the computing formula for the harmonic parameter estimation are given as well.The simulating result demonstrates that the improved algorithm holds a very high precision wien used for the unsynchronized sample sequence.

A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application

Abstract: In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT (R8-FFT) unit and an efficient data-swapping method based output buffer unit The whole chip systematic performance concerning about the area, power, latency and pending cycles for the application of IEEE 802.11a WLAN standard has been analyzed. The proposed R8-FFT unit utilizing the symmetry property of the matrix decomposition achieves half computation-complexity and less power consumption compared with the recently proposed FFT/IFFT designs. On the other hand, applying the proposed data-swapping method, a low-cost and low-power output buffer can be obtained. So as to further increase system performance, we propose one scheme: the multiplication-after-write (MAW) method. Applying MAW method with R8-FFT unit, the resulting FFT/IFFT design not only leads to the balancing pending cycle, but also abbreviating computation latency to 8 clock cycles. Consequently, adopting the above proposed two units and one scheme, the whole chip consumes 22.36mW under 1.2V@20 MHz in TSMC 0.13 1P8M CMOS process.

The Fast Fourier and Hilbert-Huang Transforms: A Comparison

Abstract: The conversion of time domain data via the fast Fourier (FFT) and Hilbert-Huang (HHT) transforms is compared. The FFT treats amplitude vs. time information globally as it transforms the data to an amplitude vs. frequency description. The HHT is not constrained by the assumptions of stationarity and linearity, required for the FFT, and generates both amplitude and frequency information as a function of time. The behavior and flexibility of these two transforms are examined for a number of different time domain signal types.

Memory-efficient and high-speed split-radix FFT/IFFT processor based on pipelined CORDIC rotations

Abstract: The author presents a CORDIC-based split-radix fast Fourier transform (FFT)/inverse FFT (IFFT) processor dedicated to the computation of 2048/4096/8192-point discrete Fourier transforms (DFTs). The arithmetic unit of a butterfly processor and a twiddle factor generator are based on a CORDIC algorithm. An efficient implementation of the CORDIC-based split-radix FFT algorithm is demonstrated. The chip of 2048/4096/8192-point FFT/IFFT core processor is fabricated in a 0.18 µm CMOS technology. The core size is 4860×7883 µm2 and contains about 200 822 gates for logic and memory, and the power dissipation is 350 mW with a clock rate of 150 MHz at 1.8 V. All control signals are generated internally on-chip. The processor performs 8192-point FFT/IFFT every 138 µs and 2048-point FFT/IFFT every 34.5 µs, respectively, which exceeds orthogonal frequency division multiplexer symbol rates. The modified-pipelining CORDIC arithmetic unit is employed for complex multiplication. A CORDIC twiddle factor generator is proposed and implemented for reducing the size of ROM required for storing the twiddle factors. Compared with conventional FFT implementations, the power consumption is reduced by 25%.

Fast fourier transform twiddle multiplication

Abstract: An FFT engine implementing a cycle count method of applying twiddle multiplications in multi-stages. When implementing a multistage FFT, the intermediate values need to be multiplied by various twiddle factors. The FFT engine utilizes a minimal number of multipliers to perform the twiddle multiplications in an efficient pipeline. Optimizing a number of complex multipliers based on an FFT radix and a number of values in each row of memory allows the FFT function to be performed using a reasonable amount of area and in a minimal number of cycles. Strategic ordering and grouping of the values allows the FFT operation to be performed in a fewer number of cycles.

A new design of carrier interferometry OFDM with FFT as spreading codes

Abstract: In this paper, we propose a new design of efficient carrier interferometry orthogonal frequency division multiplexing (CI/OFDM) by using fast Fourier transform (FFT) as spreading codes. First, we propose the use of both positive and negative frequency of the IFFT rather than only using the positive part as in conventional method. It results new CI/OFDM waveforms which only requires a half of FFT points. Second, we replace CI spreading with FFT for achieving lower complexity because complexity of CI is similar to that of discrete Fourier transform (DFT). Our results confirm that the proposed design is capable of achieving high efficiency and low complexity while providing high performance.

Azimuth fractional transformation of the fractional chirp scaling algorithm (FrCSA)

Abstract: The fractional chirp scaling algorithm (FrCSA) is based on the use of the fractional Fourier transform (FrFT) within the chirp scaling algorithm (CSA). In this paper, a closed-form expression for the azimuth FrFT of the FrCSA is mathematically derived and analyzed from the high-resolution synthetic aperture radar imaging point of view. The azimuth-FrFT expression of the FrCSA is compared to that of the classical fast Fourier transform (FFT)-based CSA. As the FFT is a special case of the generalized FrFT, the derived expression is found to be in total agreement with that of the FFT-based CSA when the transformation order is equal to unity; that is the angle of rotation is equal to pi/2

The "Invaders' Algorithm: Range of Values Modulation for Accelerated Correlation

Abstract: In this paper, we present an algorithm that allows the simultaneous calculation of several cross correlations. The algorithm works by shifting the range of values of different images/signals to occupy different orders of magnitude and then combining them to form a single composite image/signal. Because additional signals are placed in the space usually occupied by a single signal, we call this the "invaders algorithm," to imply that extra signals invade the space that normally belongs to a single signal. After correlation is performed, the individual results are recovered by performing the inverse operation. The limitations of the algorithm are imposed by the finite length of the mantissa of the hardware used, the precision of the algorithm that performs the cross correlation (e.g., the precision of the fast Fourier transform (FFT)) and by the actual values of the images/signals that are to be combined. The algorithm does not require any special hardware or special FFT algorithm. For typical 250 times 256 images, an acceleration by a factor of at least two in the calculation of their cross correlations is guaranteed using an ordinary PC or a laptop. As for smaller sized templates, tenfold accelerations may be achieved

Achieving efficient polynomial multiplication in fermat fields using the fast Fourier transform

Abstract: We introduce an efficient way of performing polynomial multiplication in a class of finite fields GF(pm) in the frequency domain. The Fast Fourier Transform (FFT) based frequency domain multiplication technique, originally proposed for integer multiplication, provides an extremely efficient method for multiplication with the best known asymptotic complexity, i.e. O(n log n log log n). Unfortunately, the original FFT method bears significant overhead due to the conversions between the time and the frequency domains, which makes it impractical to perform multiplication of relatively short (160 - 1024 bits) integer operands as used in many applications. In this work, we introduce an efficient way of performing polynomial multiplication in finite fields using the FFT. We show that, with careful selection of parameters, all the multiplications required for the FFT computations can be avoided and polynomial multiplication in finite fields can be achieved with only O(m) multiplications in addition to O(m log m) simple shift, addition and subtraction operations. We show that, especially in constrained devices where multiplication is expensive, polynomial multiplication in the suggested finite fields using the FFT outperforms both the schoolbook and Karatsuba methods for practically small finite fields, e.g., relevant to elliptic curve cryptography.

A Reconfigurable Butterfly Architecture for Fourier and Fermat Transforms

Abstract: Reconfiguration is an essential part of Soft- Ware Radio (SWR) technology. Thanks to this technique, systems are designed for change in operating mode with the aim to carry out several types of computations. In this SWR context, the Fast Fourier Transform (FFT) operator was defined as a common operator for many classical telecommunications operations [1]. In this paper we propose a new architecture for this operator that makes it a device intended to perform two different transforms. The first one is the Fast Fourier Transform (FFT) used for the classical operations in the complex field. The second one is the Fermat Number Transform (FNT) in the Galois Field (GF) for channel coding and decoding.

Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation

Abstract: This paper proposes the new radix-2 4 FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-2 2 algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35μm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.

Split-radix FFT/IFFT processor

Abstract: This invention presents a CORDIC-based split-radix FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform) processor dedicated to the computation of 2048/4096/8192-point DFT (Discrete Fourier Transform). The arithmetic unit of butterfly processor and twiddle factor generator are based on CORDIC (Coordinate Rotation Digital Computer) algorithm. An efficient implementation of CORDIC-based split-radix FFT algorithm is demonstrated. All control signals are generated internally on-chip. The modified-pipelining CORDIC arithmetic unit is employed for the complex multiplication. A CORDIC twiddle factor generator is proposed and implemented for saving the size of ROM (Read Only Memory) required for storing the twiddle factors. Compared with conventional FFT implementations, the power consumption is reduced by 25%.

The Cylindrical Taylor-Interpolation FFT Algorithm

Abstract: The cylindrical Taylor-interpolation FFT (TI-FFT) algorithm for the computation of the near-field and far-field in the "quasi-cylindrical" geometry has been developed. The cylindrical modal expansion of the vector potential is shown to be in the form that can make use of the cylindrical TI-FFT. The near-field on an arbitrary cylindrical surface is obtained from the vector potential and through the inverse FFT (IFFT). The far-field is obtained through the near-field far-field (NF-FF) transform. The cylindrical TI-FFT is valuable for back-scattering problems and "quasi-cylindrical" geometry. Like the planar TI-FFT algorithm, the cylindrical TI-FFT algorithm also has advantages of a N2 log2 N2 computational complexity, a low sampling rate, no basis functions and free of singularity problems.

An efficient fast full search block matching algorithm using FFT algorithms

Abstract: Summary Motion estimation is the most computationally expensive operation in the coding and transmitting of video streams, and the search for efficient motion estimation (in terms of computational complexity and compression efficiency) algorithm has been a challenging problem for years. The challenge is to decrease the computational complexity of the full search as much as possible without losing too much performance and quality at the output. In this paper, we propose a fast algorithm which achieves exactly the same optimal result as the direct full search algorithm. The key idea is to express a robust matching criteria sum square difference (SSD) in terms of cross correlation operations. Speed is obtained from computing the cross correlations in the frequency domain via the Fast Fourier Transform (FFT).

Fast evaluation of trigonometric polynomials from hyperbolic crosses

Abstract: The discrete Fourier transform in d dimensions with equispaced knots in space and frequency domain can be computed by the fast Fourier transform (FFT) in $${\cal O}(N^d \log N)$$ arithmetic operations. In order to circumvent the ‘curse of dimensionality’ in multivariate approximation, interpolations on sparse grids were introduced. In particular, for frequencies chosen from an hyperbolic cross and spatial knots on a sparse grid fast Fourier transforms that need only $${\cal O}(N \log^d N)$$ arithmetic operations were developed. Recently, the FFT was generalised to nonequispaced spatial knots by the so-called NFFT. In this paper, we propose an algorithm for the fast Fourier transform on hyperbolic cross points for nonequispaced spatial knots in two and three dimensions. We call this algorithm sparse NFFT (SNFFT). Our new algorithm is based on the NFFT and an appropriate partitioning of the hyperbolic cross. Numerical examples confirm our theoretical results.

Performance Models and Search Methods for Optimal FFT Implementations

Abstract: This thesis considers systematic methodologies for finding optimized implementations for the fast Fourier transform (FFT). By employing rewrite rules (e.g., the CooleyTukey formula), we obtain a divide and conquer procedure (decomposition) that breaks down the initial transform into combinations of different smaller size sub-transforms, which are graphically represented as breakdown trees. Recursive application of the rewrite rules generates a set of algorithms and alternative codes for the FFT computation. The set of "all" possible implementations (within the given set of the rules) results in pairing the possible breakdown trees with the code implementation alternatives. To evaluate the quality of these implementations, we develop analytical and experimental performance models. Based on these models, we derive methods dynamic programming, soft decision dynamic programming and exhaustive search to find the implementation with minimal runtime. Our test results demonstrate that good algorithms and codes, accurate performance evaluation models, and effective search methods, combined together provide a system framework (library) to derive automatically fast FFT implementations.

Faster than the FFT: The chirp-z RAG-n Discrete Fast Fourier Transform

Abstract: DFT and FFTs are important but resource intensive building blocks and have found many application in communication systems ranging from fast convolution to coding of OFDM signals. It has recently be shown that the n-Dimensional Reduced Adder Graph (RAG-n) technique is beneficially in many applications such as FIR or IIR filters, where multiplier can be grouped in multiplier blocks. This paper explores how the RAG-n technique can be applied to DFT algorithms. A RAG-n fast discrete Fourier transform will be shown to be of low latency and complexity and posses a VLSI attractive regular data flow when implemented with the Bluestein chirp-z algorithm. VHDL code synthesis results for Xilinx Virtex II FPGAs are provided and demonstrate the superior properties when compared with Xilinx FFT IP cores. Index Terms – Fast Fourier Transform, OFDM, FPGA, n-Dimensional Reduced Adder Graph

A Novel VLSI Architecture for Image Compression

Abstract: In analog signal processing of multimedia applications, audio need not be compressed but video must be compressed in order to conserve the bandwidth. For this purpose fast cosine transform (FCT) is preferred, which is developed using fast Fourier transform (FFT). But it has several limitations of delays, area and power. In this paper the similarities among fast Fourier transform (FFT), fast cosine transform (FCT) and fast Hartley transform (FHT) have been studied. The converged very large scale integration (VLSI) architecture for these hybrid transforms for video compression are designed, simulated and synthesized. Implementing FCT, FFT, and FST from fast Hartley transform is developed and hybrid transforms architecture is proposed. Further more, delays and area overheads have been calculated. For all these transforms the layouts have been drawn using magma tools with 0.13 mum technology. Compression ratio for image with each transform and Hybrid transform is also implemented

R2²SDF FFT Implementation with Coefficient Memory Reduction Scheme

Abstract: Fast Fourier transform (FFT) is a key building block for orthogonal frequency division multiplexing (OFDM) systems. Due to the development of wireless portable devices, it is important to minimize the size and power of a FFT processor. One of the methods to satisfy such demands is reducing the size of twiddle coefficient memory. This paper presents an effective coefficient memory reduction scheme for a R22SDF FFT implementation. When applying a conventional method to an N- point R22SDF FFT, the number of twiddle coefficients is 3N/4. However, the proposed scheme requires only (N/8+1) coefficients and its additional hardware architecture is very simple. The effectiveness of the proposed method is verified by implementation results on a FPGA.

Computational Complexity Analysis of FFT Pruning - A Markov Modeling Approach

Abstract: The Fourier transform is instrumental in many signal processing applications such as digital filtering, spectral analysis and communications. In 1965, Cooley and Tukey demonstrated that the discrete Fourier transform (DFT) can be computed using the fast Fourier transform (FFT) algorithm with reduced computational complexity. When the input vector to the FFT contains mostly zeros (i.e., is sparse), it is possible to realize computational savings over a full FFT by only performing the arithmetic operations on non-zero elements. That is, the FFT is "pruned" so that only the useful computations are performed. In this paper, we derive the (non-stationary) Markov process that describes the number of occupied (i.e. non-zero) paths at each stage of a pruned FFT. With the probability distribution of the number of non-zero paths at each FFT stage, we then determine the probability distribution of the number of multiplications and additions necessary to compute the FFT of an input vector with a given sparsity distribution

Estimation of electrical harmonic parameters by using the Interpolated FFT algorithm based on Blackman window.

Abstract: A thorough research on the high-accuracy estimation for the electrical harmonic parameters by using the Interpolated FFT algorithm was conducted.The window type and width are the main factors influencing the analysis precision.After analyzing the common windows and electrical signals,the Blackman window was more suitable for the analysis of electrical signals and the Interpolated FFT algorithm was given as well.Simulation result showed that given the Interpolated FFT algorithm based on Blackman window,the estimation precision of electrical signals' frequencies,amplitudes and phases met the state standard.

A fast fourier transform algorithm to estimate carrier frequency deviation

Abstract: Based on the maximum-likelihood parameter estimation approach, a Fast Fourier Transform (FFT) algorithm is proposed in this paper. The proposed algorithm can directly calculate the absolute value of carrier frequency-deviation, and the precision of the proposed algorithm is independent of the input Signal-to-Noise. The proposed algorithm can be used to demodulate high data rate and bandwidth efficient QPSK signal, which is used in Tracking and Data Relay Satellite System(TDRSS).

On the odd-DFT and its applications to DCT/IDCT computation

Abstract: In this correspondence, efficient algorithms are presented for simultaneous calculation of the odd discrete Fourier transform (odd-DFT) and the real DFT. These algorithms are used to derive a new algorithm to calculate the discrete cosine transform (DCT) that is computationally equivalent to the classical fast Fourier transform (FFT)-based algorithm for DCT calculation . In addition, odd-DFT properties are exploited to develop a novel algorithm for an inverse discrete cosine transform (IDCT) calculation that outperforms previous FFT-based solutions for IDCT calculation

Specialising for High Performance FFT Algorithms Based on Fixed-Point DSP

Abstract: During FFT computation, energy leakage and picket-fence effect are the most critical error sources derived from FFT algorithms; meanwhile, data truncation and rounding during the butterfly calculation implemented by fixed-point DSP can make even more significant error due to finite wordlength. Based on some established FFT spectrum correction algorithms, an improved double-windowing method is presented, and an extended-precision FFT scheme for fixed-point DSP application is put forward. The feasibilities of the two reformative methods are discussed theoretically, and the validities are testified by the simulation results

A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs

Abstract: In this paper, the grouped scheme is specially applied to compute the fast Fourier transform (FFT) when the portions of transformed outputs are calculated selectively. The grouped FFT algorithm applies the scheme of the grouped frequency indices to accelerate the computation of selected DFT outputs. The advantage of the grouped FFT algorithm is that it is more cost-effective than the convenient FFT algorithms when the authors need to compute parts of the transformed outputs, not all outputs. For computing all transformed outputs of the DFT, the computational complexity of the proposed FFT method is less than that of the radix-2 method. Meanwhile, the computational complexity of the proposed fast method approximates to that of the radix-4 FFT algorithm. By sharing coefficients of the twiddle factors in the same frequency group, the grouped FFT can be implemented with hardware sharing VLSI architectures

A Fast Address Generation Scheme for FFT Processor

Abstract: A fast address generation scheme of radix r(r=2,4,8,…) Cooley-Tukey fast Fourier transform(FFT) algorithm for fixed point and variable point is proposed.The new scheme is based on the r number system and it's calculating rule.The advantage of this address generation scheme lies in that it generates fast the operation and twiddle factors address and further reduces the twiddle factors access times and compresses the twiddle factors' storage volume in variable point FFT processor.