Showing papers on "Static induction transistor published in 1982"

Velocity-Modulation Transistor (VMT) : A New Field-Effect Transistor Concept

Abstract: Field-effect transistors of a completely new category are proposed and analysed, in which the conductivity modulation ΔG by the gate voltage Vg is brought forth mainly through the Vg-dependence of electron mobility. Since the sheet concentration of electrons in such FETs need not be modulated, the switching speed of the device is expected to be free from the transit time limitation, reaching the range of subpicosecond. As a specific example, an FET with a dual-channel configuration is discussed.

Channel-collector transistors

Abstract: By merging the channel regions of two-junction field-effect transistors with the collector region of a bipolar junction transistor (BJT), one achieves a quasi-cascode configuration called a Channel-Collector Transistor (CCT). Its terminal properties are those of a modified, improved bipolar transistor. Prototype devices have been fabricated with common-emitter current gain (β F ) in excess of 1200 while still maintaining the common-emitter, open-base breakdown voltage (BV CE0 ) greater than 140 V and the output resistance r 0 typically greater than 200 kΩ. The present brief describes an efficient, qualitative equivalent circuit for the structure and also presents an experimental device graphically illustrating the CCT's advantages and disadvantages when compared to a conventional BJT.

Common memory gate non-volatile transistor memory

Abstract: A non-volatile semiconductor memory is described incorporating a fixed threshold transistor and a variable threshold transistor in each memory cell. The fixed threshold transistor is used for row selection while the variable threshold transistor stores the data. A common memory gate line throughout the memory permits block erase to one logic state with opposite data being written in on a row-by-row basis. Information is read out from a selected row by a ramp voltage on the memory gate line which is capacitively coupled through variable threshold transistors having a channel in the body below the gate region.

Field effect transistor with high cut-off frequency and process for forming same

Abstract: There is disclosed a heterojunction field effect transistor with an accumulation of majority carriers functioning as a high cut-off frequency device in which the transistor uses the properties of the same type GaAs/Al x Ga 1-x As N-doped junctions with the GaAs being weakly doped. This is used to produce a high mobility of charges in the accumulation layer and is effected by a structure in which the source and drain regions are partially covered by the gate region which is in turn covered by an insulation layer and thereby reduces the access resistances and increases the transition frequencies.

A three-dimensional analysis of semiconductor devices

Abstract: An accurate three-dimensional analysis of semiconductor devices based on the general transport equations is carried out. In this analysis, the finite difference formulation and ICCG (Incomplete Choleski and Conjugate Gradient) methods are utilized to reduce computational time and memory requirements. The algorithms are applied to a wide variety of devices, including a bipolar n-p-n transistor, an Integrated Injection Logic (ILL), and a Static Induction Transistor (SIT). Calculated results are compared to those obtained using a conventional two-dimensional simulator. Several three-dimensional effects are modeled successfully. These analyses make it clear that three-dimensional calculation is indispensable for accurate device modeling.

Overcurrent limiter circuit for switching regulator power supplies

Abstract: A circuit is disclosed which provides overcurrent protection for switching regulator power supplies with soft start and soft turn OFF features. The invention includes first means for sensing the current through the switching transistor of the regulator and second means for providing a voltage signal to the switching transistor deactivation circuitry whenever the current through the switching transistor exceeds a predetermined threshold. In a specific embodiment, the current generator is provided by a transistor biased for nominal operation in its active mode. The means for sensing the current through the switching transistor is provided by a resistor the voltage drop across which provides the input voltage threshold to the bipolar transistor current generator. The current generated by the transistor causes a voltage to quickly develop across an RC network referenced to ground potential. This voltage is then compared to a reference potential by a comparator circuit which provides an electrical signal as an input to the base drive circuit for the switching regulator switching transistor.

High performance MESFET transistor for VLSI implementation

Abstract: A gallium arsenide buffer amplifier for use in a very large scale integrated circuits is provided. The transistor device in the buffer amplifier has a uniform depth N+ source, gate and drain region and the N+ dopant concentration is made very high which effectively reduces the resistance of the transistor device and permits the area of the device to be reduced by more than one order of magnitude while maintaining high current and power levels.

Second breakdown of vertical power MOSFET's

Abstract: It is shown that a phenomenon of second breakdown similar to that in bipolar transistors can occur in vertical power MOSFET's. A model for the phenomenon of second breakdown involving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and base resistance is proposed. After presenting the theory, this model is compared with experiments on four-terminal V-groove test devices in which the substrate can be accessed independently. Good agreement is achieved between calculated and measured boundaries of the safe operating area. The model should be applicable to DMOS devices as well.

Dual mode power transistor

Abstract: A dual mode power transistor circuit is provided for optimizing ON state dissipation, base drive requirements, and switching speed in applications subject to large overload currents for short periods of time. The circuit has dual modes or regions of operation: (1) rated current and below; and (2) overload current. In the overload region, additional base drive is supplied to the bipolar power transistor while also keeping such transistor in its active region, out of saturation, to enable fast turn-off. The additional base drive is supplied at a given sensed current-induced threshold voltage and enables the transistor to conduct increased collector current therethrough, which in turn reduces the otherwise increased collector to emitter voltage. Turn-off power dissipation is substantially reduced, in spite of the increased collector current, due to the drastically reduced collector to emitter voltage. Particularly simple dual mode Darlington-like transistor circuitry is disclosed. Bidirectional dual mode transistor circuitry is also disclosed.

High efficiency push-pull inverters

Abstract: High efficiency push-pull inverters minimize undesirable energy losses usually resulting from simultaneous conduction and imperfect switching of the transistor switching means In each of the disclosed circuits, a saturable inductor and a diode are connected in parallel and across the base-emitter junction of each transistor Voltage on the base of each transistor causes its associated saturable inductor to saturate, and the saturated inductor then terminates the flow of base current and provides a path for rapid evacuation of the charge carriers stored in the transistor base-emitter junction in order to render the transistor rapidly non-conductive Each diode provides a drain path for current continuing to flow through its associated saturable inductor after junction evacuation A novel triggering means initiates oscillation of the inverters Also disclosed are feedback means operable to prevent premature transistor conduction and a capacitor connected between the collectors of the inverter transistors operable to restrain the rate of change of transistor collector voltage, both of these features also serving to minimize energy dissipation Iadd

Stacked MOS transistor

Abstract: In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part (18, 20, 22) formed in a silicon substrate (12) and an upper part (30, 32, 26) composed of recrystallized polysilicon. The device gate (24) is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.

Monolithically merged field effect transistor and bipolar junction transistor.

Abstract: Semiconductor device comprising a monolithically merged field-effect transistor and bipolar junction transistor. The device has a semiconductor region (28a) with a base contact (13) and a gate electrode (15) such that a signal applied to the base contact (13) causes the device to function as a bipolar junction transistor, while a signal applied to the gate electrode (15) causes the device to function as a field-effect transistor. In this manner, the mode of operation may be chosen so as to achieve the most desired operating characteristics.

Static induction transistor image sensor with noise reduction

Abstract: A SIT (Static Induction Transistor) image sensor with a high-sensitivity and a high-fidelity is disclosed. The image sensor comprises a SIT image cell array and a scanning circuit which scans in turn a plurality of SIT image cells in such a manner that respective scanning time in all the cells are equal throughout a sequential scanning operation for the SIT image sensor. A reading line and a refreshing line may be combined into a single line. A differential amplifier is provided for correcting a picture element information to remove a noise component therefrom.

Circuit arrangement for controlling a power field-effect switching transistor

Abstract: A power field-effect switching transistor is switched-on by charging its gate-source capacitance by connecting a capacitor thereto by means of a first transistor. Switching-off of the power field-effect switching transistor is achieved by discharging the gate-source capacitance by switching-on a second transistor. In this manner, the charging and discharging processes take place at low resistance, and therefore in a short period of time. As a result, switching times and switching power losses for the power field-effect switching transistor are minimized. In addition, the need for a separate auxiliary voltage source and inductive circuit elements is obviated.

MOS transistor circuits having matched channel width and length dimensions

Abstract: The voltage gain of an MOS transistor inverter stage is made independent of the device threshold voltages and of channel lengths by making the length and width of the channel region of the upper load transistor equal to the length and width of the channel region of the lower driver transistor.

Current source circuit for producing a small value output current proportional to an input current

Abstract: A series circuit consisting of the emitter-collector path of a first transistor of npn type and an input current source is connected between a negative voltage source and a positive voltage source. Another series circuit consisting of the emitter-collector path of a second transistor of npn type and the collector-emitter path of a fourth transistor of pnp type is also connected between the negative and positive voltage sources. A further series circuit consisting of a first resistor, the emitter-collector path of a third transistor of npn type, a second resistor, and the collector-emitter path of a fifth transistor of pnp type is connected between the negative and positive voltage sources. The second and third transistors have their bases connected together. The fourth and fifth transistors have their bases connected together. The collector of the first transistor is connected to the base of the fifth transistor. The base of the first transistor is connected to the emitter of the sixth transistor. A seventh transistor has the emitter connected to the negative voltage source, the base connected to the collector of the third transistor and the collector connected to an output current terminal. The fourth and fifth transistors have an equal emitter area, and the ratio of the emitter area of the third transistor to the emitter area of the second transistor is set to m(m>1). The ratio of the output current to that of the current source is less than unity. This ratio is determined solely by the ratio m and the ratio between the resistances of the first and second resistors and is free from any temperature coefficient.

Sense amplifier for a dynamic RAM

Abstract: A single ended sense amplifier (10) receives a bit line signal (16) at the gate of a detector MOS transistor (36). The source of the detector transistor (36) is connected to a reference voltage (24) which is adjusted prior to each memory cycle to make the gate to source voltage of the detector transistor (36) equal to the approximate threshold voltage of the transistor. The drain of the detector transistor (36) gates an amplifier transistor (30) which inhibits or passes a read signal (18) to the gate of a digit line pull down transistor (32) which provides an active pull down on a digit line (26) that is precharged to a high voltage prior to a memory read cycle.

Mos power transistor

Abstract: MOS power transistor (10) having a high breakdown voltage and reduced on-state resistance of conduction. The transistor (10) is of a channel type diffuse having source electrodes (32) and gate (28) on a first surface (24) and a drain electrode (34) on a second surface. a voltage high breaking is obtained by fabricating the device in a high resistivity epitaxial layer (14) having a doping level corresponding to the voltage required rupture. The reduced resistance to the conduction state is obtained by locally reducing the resistivity of the epitaxial layer (14) in surface regions (44) disposed between two adjacent source regions (20).

The lateral punch-through transistor

Abstract: Operation of a diffused-gate, lateral punch through transistor has been demonstrated. Operation is similar to the static induction transistor, and the device can be used in planar integrated circuits. Current flow in this lateral device obeys the space charge limited conduction law over a wide range of currents, and the drain current exhibits a negative temperature coefficient.

Gallium arsenide static induction transistor

Abstract: A gallium arsenide static induction transistor of normally-off type simple in manufacture and exhibiting a superior function and suitable for use in low and medium power operation in integrated circuit is obtained by arranging so that its channel region has a length l (μm), a width (μm) and an impurity concentration N (cm -3 ), and that the ratio l/w is 0.5-5.0 and that the product Nw 2 is not larger than 2.5×10 15 cm -3 .μm 2 .

FET-bipolar switching device and circuit

Abstract: A switching device and circuit comprises a bipolar transistor and at least two field effect transistors for controlling the bipolar transistor. A first field effect transistor has its drain and source connected across the collector-base of the bipolar transistor and a second field effect transistor has its drain and source connected across the base-emitter of the bipolar transistor. Gates of the first and second field effect transistors are connected in common and supplied with a voltage signal. The first field effect transistor is of an enhancement type and the second field effect transistor is of a depletion type.

MOSFET buffer circuit with an improved bootstrapping circuit

Abstract: A semiconductor circuit has first and second MOS transistors which are connected between an output terminal and a positive and a reference power source terminal, respectively, a bootstrap capacitor connected between the output terminal and the gate of the first MOS transistor, an inverter which inverts the input signal and which supplies the inverted signal to the gate of the second MOS transistor after a predetermined delay timne, and a switching MOS transistor having a current path connected between the input terminal and the gate of the first MOS transistor. The switching MOS transistor has a threshold voltage greater than that of the second MOS transistor.

Normally-off type high speed SI-Thyristor

Abstract: The design, fabrication, and characterization of a normally-off type static induction thyristor (SIThy) with a surface gate structure were made with an intention to use it in high speed switching at high currents. The device chip had a size of 7 × 10 mm2and included 9,000 channels, where each channel stripe had a width of 1.5 \micro m and a length of 250 \micro m. The double LOCOS technique was used in the fabrication process of the device. By mounting the chips in specially designed packages, a very low forward voltage drop of 1.2 V at 100 A and a high switching speed of 300 ∼ 600 nsec in turn-on and turn-off times were obtained. A bipolar mode static induction transistor (BSIT) was also made by using the same photomasks and the same fabrication process as SIThy. It also exhibited a low forward voltage drop of 0.7 V at 100 A and a high switching speed of 100 ∼ 200 nsec in turn-on and turn-off times.

CMOS-Bipolar Darlington device

Abstract: A semiconductor device having in a semiconductor body a Darlington amplifier comprising a vertical enhancement VMOS-transistor (T1) as input transistor and a vertical bipolar power transistor (T2) as output transistor. In order to increase the switching speed, a lateral enhancement MOS transistor (T3) of complementary conductivity type to the first transistor (T1) is connected in parallel with the emitter-base junction of the bipolar output transistor (T2). The gate electrodes of the first and second transistors are interconnected and associated with an input terminal E. Double and treble epitaxial layer structures are disclosed for integrating the device in the semiconductor body. The lateral third transistor (T3) may be provided either within or outside the area of an epitaxial layer forming the emitter zone of the second transistor (T2).

Single-ended push-pull induction heating apparatus

Abstract: An induction heating apparatus comprises an SEPP inverter including two transistors (Q1, Q2) connected in series, one transistor (Q1) being connected to a high electric potential end of a direct current power source (DB1) and the other transistor (Q2) being connected to a low electric potential end. A series circuit of a induction heating coil (L1) and a resonance capacitor (C1) is connected in parallel with one transistor (Q1) and freewheel diodes (D1, D2) are connected in anti-parallel with two transistors (Q1, Q2), respectively. A controlling circuit (71) turns one transistor (Q1) on/off in a predetermined cycle and a controlling circuit (72) turns the other transistor (Q2) on in an arbitrary time period in an off interval of one transistor (Q1) so that an input current to the series circuit is controlled.

Semiconductor device having a safety device

Abstract: Semiconductor device having a safety device (4) comprising an improved lateral bipolar transistor structure (5). The improvement is obtained by incorporating an auxiliary field effect transistor (6) which has the emitter (8) as source zone and the collector (9) as drain zone and in which the threshold voltage of the auxiliary field effect transistor is lower than the avalanche breakdown voltage of the collector- base junction of the lateral transistor. As a result of this the lateral transistor switches sooner, at a lower voltage, to the readily conductive on-state.

Protection circuit for an output transistor

Abstract: A protection circuit for an output transistor which produces a protecting signal representing the power consumption of the output transistor (52), namely the product of collector current and collector to emitter voltage of the output transistor, thereby protecting the output transistor over a broad operating range.

Characteristics of high-power and high-breakdown-voltage static induction transistor with the high maximum frequency of oscillation

Abstract: The design and fabrication of high-power and high-breakdown-voltage static induction transistor (SIT) with a high maximum frequency of oscillation are described and then the experimental characteristics are presented. A field plate is used to make the breakdown voltage high, and a fine stripe structure is adopted to make the maximum frequency of oscillation high. As a result, the gate-drain breakdown voltage of 300 V, the gate-source breakdown voltage of 70 V, and the maximum frequency of oscillation of 700 MHz are obtained. The maximum output power of 216 W with 7.5-dB gain and 55- percent drain efficiency is obtained at 100 MHz without a thermal runaway from an amplifying SIT with four pellets mounted in a single package.

I2 L Structure and fabrication process compatible with high voltage bipolar transistors

Abstract: An integrated circuit wherein the base and surface collector regions of the I2 L vertical transistor are formed by the same steps used to form the collector and base, respectively, of complementary bipolar transistors. Thus, a high voltage bipolar transistor of the same type as the vertical I2 L transistor may be formed using separate process steps, thereby optimizing the design of both devices.

A vertically isolated self-aligned transistor—VIST

Abstract: A vertically isolated self-aligned transistor (VIST) has been developed to make possible high-speed low-power dissipation bipolar devices suitable for LSI. This VIST consists of a bird's beak free oxide isolated structure and a high impurity density inactive base self-aligned to the polysilicon emitter. A flat emitter transistor with a self-aligned base is developed by forming an inactive high impurity density base region with an ion-implantation method using a polysilicon emitter as a mask. The transistors exhibit uniform current gain even to current levels as low as 10-8A. The f t value of this transistor is 6 GHz. The ring oscillators and counter are fabricated using the 13 × 6 µm2transistor cell. The power and delay product is 0.12 pJ.