Showing papers on "Strained silicon published in 1976"

MIS semiconductor device and method of manufacturing the same

Abstract: A metal-insulator semiconductor (MIS) device is manufactured by initially forming, on a semiconductor substrate, an insulating film having a hole therethrough and depositing silicon on the substrate to form a first monocrystalline silicon film in the hole and a polycrystalline silicon film on the insulating film. Then, a further insulating film is formed on the first silicon film, and a second silicon film is formed on the further insulating film. The second silicon film and the further insulating film are removed, so that the monocrystalline and polycrystalline parts of the first silicon film are exposed at both sides of the remaining part of the second silicon film and the further insulating film. Finally, an impurity is diffused to form a source and a drain region in the monocrystalline silicon film and conductive layers of polycrystalline silicon are disposed contiguous to the source and drain regions.

Method of manufacturing a semi-insulating silicon layer

Abstract: Silicon ions are implanted in a silicon dioxide layer on a silicon substrate so that the dioxide layer is converted into a semi-insulating layer having an improved passivation property.

Silicon resistive device for integrated circuits

Abstract: A resistive device for use as a current feedback loop in an integrated CMOS shift register circuit is made of an island of polycrystalline silicon with a sheet resistivity of from 10 6 to 10 8 ohms per square. The polycrystalline silicon island has two contacts thereon fashioned in the manner of MOS source and drain contacts and a dummy polycrystalline silicon insulated gate contact thereon. The device structure is designed to be and is fully compatible with CMOS mesa processing. The method for making the device incorporates into the processing steps for CMOS manufacture the formation of polycrystalline silicon islands on the substrate along with monocrystalline silicon islands. In the process, the polycrystalline silicon island is doped, through source and drain mask openings, with impurities of the same conductivity type as that predominating in the polycrystalline silicon island.

Formation of metal nitride oxide semiconductor (MNOS) by ion implantation of oxygen through a silicon nitride layer

Abstract: A layer of silicon nitride (Si 3 N 4 ) is deposited on a silicon substrate. A mask provided with windows representing device structures is then formed over the silicon nitride layer. Oxygen is then implanted through the window portion of the silicon nitride layer into the Si 3 N 4 /Si interface region to form a tunneling insulator interface layer of silicon dioxide (SiO 2 ). The final structure is heat treated and then has the form Si 3 N 4 /SiO 2 /Si. It can be made into a metal nitride oxide semiconductor (MNOS) field effect transistor device by conventional diffusion, ion implant and metallization processes.

Silicon oxide/silicon nitride mask with improved integrity for semiconductor fabrication

Abstract: A semiconductor dielectric layer formed of silicon nitride having a uniform dispersion of carbon therein for providing reduced intrinsic tensile stresses of less than 10 × 10 9 dyn/cm 2 .

Minimization of misfit dislocations in silicon by double implantation of arsenic and germanium

Abstract: A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom concentration of at least 1 × 10-2 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5% smaller -- when high arsenic atom concentrations of at least 1 × 10-2 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted, then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.

Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps

Abstract: A METHOD OF FORMING AN INTEGRATED CIRCUIT REGION THROUGH THE COMBINATION OF ION IMPLANTATION AND DIFFUSION STEPS Abstract A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conduct-ivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivity-determining impurity of the same type through the same aperture into said substrate. The method has particular application when the elec-trically insulative layer is a composite of two layers, e.g., a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to pro-vide an undercut beneath the silicon nitride ion implanta-tion barrier layer.

Utilizing multiple polycrystalline silicon masks for diffusion and passivation

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first polycrystalline silicon layer containing oxygen atoms on a semiconductor layer, of forming a second polycrystalline silicon layer containing nitrogen atoms on the first polycrystalline silicon layer, of removing a predetermined part of the first and second polycrystalline silicon layers to form an opening therein, and of diffusing impurity material into the semiconductor layer through the opening in order to form a diffused region. The fabricating process can be remarkably simplified.

Process for thinning silicon with special application to producing silicon on insulator

Abstract: This disclosure relates to methods of producing thin layers of silicon as well as thin layers of silicon on insulating substrates such as silicon dioxide or polycrystalline silicon by forming either an n- layer of single crystal silicon over a p++ layer of single crystal silicon or a p- layer of single crystal silicon over an n++ layer of single crystal silicon and then removing either the n++ or p++ single crystal substrate, as the case may be, by utilizing an etch which will only etch the n++ or p++ region and will stop when the n- or p- region, as the case may be, has been reached.

Silicon Planar Devices Using Nitrogen Ion Implantation

Abstract: Nitrogen implanted polycrystalline silicon layers are used as an oxidation mask in place of conventional silicon nitride layers for the fabrication of planar structured MOS FET's. The stress effect and anomalous oxidation behavior arising from the conventional LOCOS process are thoroughly eliminated. Moreover, the lateral oxidation effect under the oxidation mask was sufficiently reduced. The threshold voltage, unit channel conductance and junction leakage current of devices having nitrogen implanted polycrystalline silicon gates are on the same level as those of conventional LOCOS type devices, which indicates that heavily implanted nitrogen has no effect on the degradation of the substrate crystal. It is also found that silicon dioxide layers behave as diffusion masks against electrically active nitrogen. Another distinct merit of this process is the elimination of the mask alignment margin between the active region and the polycrystalline silicon gate, which makes possible the consequent increase in the device packing density. These results confine the applicability of this process technology to the fabrication of MOS LSI's with a high packing density.

Two-phase continuous poly silicon gate CCD

Abstract: This invention provides the structure for a two-phase charge coupled storage device. Alternate regions of thicker and thinner silicon dioxide are grown upon a silicon substrate. These silicon dioxide regions are covered with a layer of deposited, undoped polysilicon. A layer of silicon dioxide is grown over the polysilicon. Ion implantation is applied to cause isolated regions of conductivity in the polysilicon. Then contact windows are cut in the upper most layer of silicon dioxide exposing the polysilicon therethrough and a metal coating is deposited in the contact windows. Two-phase signals are applied to the resulting electrodes to advance charges at the surface of the silicon substrate.

Method for manufacture of a semiconductor device

Abstract: OF THE DISCLOSURE A semiconductor device and method of making the same is disclosed having a surface passivation film of a polycrystalline silicon layer containing 2 to 45 atomic percent of oxygen atoms. The polycrystalline silicon layer is locally electrically insulated by oxidizing throughout the thickness of the layer. The local oxidizing treatment causes the polycrystalline or silicon layer to pattern.

Process for producing an improved dielectrically-isolated silicon crystal utilizing adjacent areas of different insulators

Abstract: Thermoprocessing of integrated-circuit devices and ionizing radiation environments create electronic charges in dielectric isolation materials and in dielectric-semiconductor interface regions. These charges can produce serious alterations in the operating characteristics of the devices and integrated circuits. The deleterious effect of these charges may be greatly reduced by the disclosed process which produces a single-crystal silicon film dielectrically isolated from a polycrystalline silicon support by an underlying insulator of either silicon nitride or silicon dioxide, both of which may be grown by the process at selected locations on the same chip.

Field effect transistor structure and method for making same

Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

Silicon-insulator-polysilicon infrared imaging device and method of making same

Abstract: A layer of epitaxial silicon is grown on a silicon growth substrate, a thinayer of silicon dioxide or other suitable insulator is grown (in the case of silicon dioxide) or deposited (for other insulators) on the epitaxial layer, and a thick layer of polysilicon is grown on the dioxide layer. The silicon growth substrate is then removed, and the epitaxial layer is etched to form islands on the insulator layer. Some of the islands are doped to form an array of infrared sensitive detectors, and a large island is doped to act as CCD region. Electrical leads are fabricated, some to provide drive and output lines for the CCDs, other to provide connections of the detectors to respective CCDs, and yet others to provide common leads for the detectors.

Electron mobility in epitaxial silicon near a sapphire substrate

Abstract: A test structure comprising an interdigital silicon network is used to obtain the silicon sheet resistance and the space‐charge capacitance adjacent to a sapphire substrate by applying distributed network analysis. The bulk carrier mobility and impurity concentration are determined from these data by a new method which is independent of interface states. An electron mobility of 1200 cm2/V sec in the silicon beyond 0.2 μ from the sapphire interface is found with a marked decrease as the interface is approached.

Radiation in MOS/SOS Devices.

Abstract: : The electrical properties of thin silicon films deposited on sapphire differ from those of bulk silicon not only because of crystalline imperfections but also because of the proximity of any point within a film to the silicon/sapphire interface. This interface often has a strong influence on SOS device characteristics, especially on the leakage current of irradiated n-channel MOS/SOS transistors. An important aspect of this program has been to define and develop experimental device structures and measurement techniques which would allow a detailed study of silicon/sapphire interfaces. The structures found most suitable for this purpose were junction field-effect transistors (JFET's) and metal-insulator-semiconductor capacitors using the sapphire substrate as gate insulator (back-gate MIS capacitors). Their design and use is described in this report. It is shown that they complement each other in establishing the pre-irradiation and post-irradiation properties of the silicon-on-sapphire films and silicon/sapphire interfaces. The parameters measured included the impurity concentration and mobility as a function of depth into the silicon films, the pre-irradiation silicon/sapphire interface charge, as well as the radiation induced interface charge and changes in the JFET channel conductance as a function of radiation dose.

Method of manufacturing silicon integrated circuits utilizing selectively doped oxides

Abstract: A method of forming buried regions in a printed circuit substrate in which; a first layer of doped silicon oxide is deposited on the substrate, a pattern of apertures is produced in this layer and a second layer of differently doped silicon oxide is deposited to fill in apertures. The first layer silicon dioxide acts as a mask to the doping material so that when the two layers are subjected to a common diffusion step both doping materials are driven into the substrate, with the second layer doping material restricted to the regions of the apertures.