Showing papers on "Switched capacitor published in 1992"

Time-domain analysis of networks with internally controlled switches

Abstract: A computer-oriented method for the time-domain analysis of networks with internally controlled ideal switches is presented No assumptions are made about the continuity of the circuit response at the switching instants; even Dirac impulses are permitted In fact, it is shown that Dirac impulses must be considered for the analysis of some switched networks, even though they may only be present for intermediate steps of the analysis Several topological changes may be needed at each switching instant to ensure that the topology after switching is valid The theories have been implemented in a computer program, SWANN The network equations are generated with a two-graph modified nodal analysis technique, rather than the state equation formulation Various internally controlled switches are permitted, such as the ideal diode, thyristor, and voltage- and current-controlled switches Numerical results show the generality and accuracy of the method on three switched networks >

Design and implementation of a high precision readout system for the ZEUS calorimeter

Abstract: The design of the readout system for the high resolution ZEUS calorimeter is described. The design employs 10 MHz switched capacitor pipelines and digital signal processors, and provides linear operation over a 17-bit dynamic range. The implementation of the design is also discussed.

Steady-state analysis and design of a switched-capacitor DC-DC converter

Abstract: A switched capacitor DC-DC power converter topology which consists of n stages of semiconductor switches and capacitors is described The switches connect the capacitors across the input source during the charging phase and then across the load during the discharge phase to step down the input voltage by a nominal ratio n Further control of the output voltage is possible via current, resistive, or duty-ratio control Based on the observation that the ripple on the capacitor voltages is generally linear in practice, state-space averaging is used to derive the average state-space equations for a generalized n-stage switched capacitor converter circuit Both exact and approximate equations which are useful for design are derived for the practical performance parameters A design procedure based on these equations is described The analytical results have been verified by extensive simulation by PSPICE >

An improved double sampling scheme for switched-capacitor delta-sigma modulators

Abstract: A switching scheme for a delta-sigma modulator (DSM) is described that allows double-sampled integrators to be used without degrading the performance of the DSM. To implement double sampling, two capacitors are required and it is impossible to assure perfect matching of these capacitors. With previously described switching methods, this capacitor mismatch causes a degradation in baseband signal-to-noise ratio. The novel switching scheme converts the capacitive mismatch into an additive out-of-band tone that has no impact on the performance of the DSM. Simulations have verified that, for arbitrary capacitor mismatches with an ideal op-amp, the improved double sampling scheme provides nearly perfect performance. >

Development of power electronics converters based on switched-capacitor circuits

Abstract: A new DC-to-DC converter is proposed that uses only switched capacitors. The energy conversion is based on controlled cyclical switching between two phases. The DC gain can be fixed by choosing an appropriate steady-state value of the duty ratio. The output voltage can be kept constant over a large range of loads. The output voltage ripple was less than 5% for most of the load range interval. By avoiding the use of magnetic elements, a small-size and lightweight converter can be built. The circuit is analyzed by using the state-space averaging method. The theoretical results have been confirmed by experimental data. >

Fundamental limitations of switched-capacitor sigma-delta modulators

Abstract: In recent years oversampling techniques have become very popular for implementing high resolution analogue-to-digital (A/D) convertors. To obtain high resolution the order of the modulator L and the oversampling ratio M are commonly seen as degrees of freedom since no theoretical limit exists for the maximum achievable signal-to-quantisation-noise ratio (SNR). However, in practical cases two fundamental constraints need to be considered in the design of the modulator, namely the thermal noise generated by the switches and the amplifiers and the settling error due to finite values of the gain-bandwidth product and the slew rate. The paper presents a closed form relation for the SNR performance of generic L-order N-bit modulators designed with switched-capacitor (SC) techniques. The relation takes into account all the above constraints. One of the major conclusions is that state-of-the-art 2nd-order SC modulators are sufficient to achieve competitive SNR performance.

Multibit bandpass delta-sigma modulators using N-path structures

Abstract: Simulation results on two switched-capacitor circuits suitable for use in a multi bit bandpass sigma-delta modulator are presented. The circuits use the N-path technique to guarantee accurate placement of the noise-transfer-function zeros. A 6th-order multibit bandpass analog-to-digital converter with a sampling frequency which is four times the center frequency and with a 5.5% bandwidth relative to the center frequency (the oversampling ratio equals 36) is described as a design example. System-level simulations, reported earlier, showed that this modulator promises a 94-dB SNR as long as the DAC (digital-to-analog converter) linearity is at least 8 b. The simulation results presented show that, in order to achieve this level of performance, the integrator circuits require high op-amp gain, and so a gain-compensated version of one of them is presented. The improved circuit requires an op-amp gain of 54 dB to achieve a modulator SNR of 90 dB. >

Tri-level capacitor structure in switched-capacitor filter

Abstract: A tri-level capacitor structure includes a first shielded metal layer (36) that is disposed between an upper metal layer (38) and a lower polysilicon layer (34). The shielded metal layer (36) is separated from the polysilicon layer (34) by an oxide layer (42), and the upper metal layer (38) is separated from the shielded layer (36) by an oxide layer (44). The upper metal layer (38) and the polysilicon layer (34) are connected together to a node (48) to form an Insensitive Node, whereas the shielded layer (36) is connected to a node (46) that is referred to as the Sensitive Node (S). The capacitor structure is operable to be connected in a switched-capacitor configuration in a lossy integrator, such that the Sensitive Node is connected to the virtual ground of a differential amplifier (50). The integrator utilizing this configuration would be comprised of at least one switched-capacitor (56) on the input that has the plates thereof connected between ground and either an input signal V IN or the inverting input of the differential amplifier (50) through control switches (62) and (64). The Sensitive Node associated with node (46) is connected to the switch (62) such that it is connected between ground and the inverting input of amplifier (50).

Noise in mixed continuous-time switched-capacitor sigma-delta modulators

Abstract: It is commonly accepted that oversampling/noise-shaping is the most suitable technique for implementing high-resolution data converters in MOS technologies. Most existing modulators use switched-capacitor (SC) techniques because they provide a highly controllable design. When compared to continuous-time (CT) techniques, SC techniques have two main drawbacks: settling time limitation and thermal noise folding. In this paper the performance of mixed continuous-time/switched-capacitor (CT-SC) and SC modulators is compared by analytically evaluating the thermal and jitter noise contributions. Relationships are derived which define the conditions for designing mixed modulators with lower levels of noise power than their SC counterparts. The main conclusion is that in mixed modulators the thermal noise can be significantly reduced, while the jitter noise could be a severe limit on the realisation of high resolution converters.

Single ended to fully differential converters

Abstract: A single to fully differential converter for fully differential switched capacitor circuits is provided which can be incorporated into a switched capacitor integrator architecture performing both conversion and integrating functions without affecting the performance of the fully differential integrator.

Method and apparatus for an improved multiple channel sensor interface circuit

Abstract: A method and apparatus for an improved multiple channel sensor interface circuit is described which comprises a plurality of input integrator circuits (35) coupled in parallel; a switched capacitor multiplexer (37) coupled to the input integrator circuits (35); and an output integrator stage (39) coupled to the switched capacitor multiplexer (37). An additional embodiment is described wherein a multiple channel voltage sensor interface circuit comprising a plurality of switched capacitor storage elements (S26 . . . S28) is coupled to a plurality of inputs; a plurality of integrator amplifiers (51, 53) is coupled to the switched capacitor storage elements (C22 . . . C30); and timing circuitry is coupled to the switched capacitor storage elements (C221 . . . C30) and to integrator amplifiers (51, 53) operable to selectively enable sampling of the inputs.

Artificial neuron with switched-capacitor synapses using analog storage of synaptic weights

Abstract: A pseudo-analog electronic or optoelectronic neuron stores synaptic weights as analog quantities, preferably as charges upon capacitors or upon the gates of floating gate transistors. Multiplication of a stored synaptic weight times a binary pulse-width-modulated synapse input signal periodically produces electrical charge of a first polarity on a first synapse capacitor. Meanwhile a fixed charge of opposite polarity is periodically produced at the same frequency upon another, second, synapse capacitor. The charges on both synapse capacitors at many synapses are periodically accumulated, and integrated, at a single neuron soma in the form of pulse-amplitude-modulated charge-encoded signals. This accumulation, and integration, transpires continuously progressively by a switched-capacitor technique, and during the entire duration of the input signal to each synapse. The net final result, expressed in signed electrical charge, is converted back to a PWM binary signal for transmission to further neurons. A fully capacitive synapse typically occupies a compact area of 45λ×42λ, consumes less than 2 μW dynamic power (at 1 MHz) and offers more than 90% of the full voltage scale for linear weight adaptation. It is therefore well suited to large scale parallel implementations of adaptive neural networks.

Capacitor in a semiconductor integrated circuit and non-volatile memory using same

Abstract: A capacitor used in a semiconductor integrated circuit, in which lower electrode 31, a ferroelectric film 33, and an upper electrode in the form of a comb are formed on the source region 13a of a field-effect transistor 10 in the stated order, to form a ferroelectric capacitor which is apparently made of a plurality of capacitors small in area which are connected in parallel to one another. Thereby, the capacitor for a semiconductor integrated circuit can store a sufficient amount of signal charge, and is short in switching time.

On-line testing of switched-capacitor filters

Abstract: Proposes a new solution to alleviate the area overhead when replication is used in switched-capacitor filters. This new approach, although based on the voter mechanism, only requires a programmable biquad and some control logic as extra components (instead of the full duplication of the system). To some extent, it can be considered a first intent to apply information redundancy for the concurrent test of analog circuits. >

Switched-capacitor notch filter with programmable notch width and depth

Abstract: A notch filter circuit includes first and second operational amplifiers, each having a capacitor connected from the amplifier output to the input. A third capacitor is connected between the second-amplifier input and the filter circuit input. A first switched-capacitor resistor is connected between the filter circuit input and the first-amplifier input. A second switched-capacitor resistor is connected between the first amplifier output and the second amplifier input. The second-amplifier output is connected to the filter circuit output. A third switched-capacitor resistor is connected between said filter circuit output and said first amplifier input; First and second programmable capacitor arrays are connected respectively in parallel with the third switched-capacitor resistor and in parallel with the first switched-capacitor resistor, so that a change only in the capacitance of the second capacitor array causes a corresponding change in the filter notch depth and a change only in the capacitance of the first capacitor array causes a corresponding change in the filter notch width. The first and second capacitor arrays each have a group of digital programming terminals that may be connected together for making fixed the ratio of the capacitance values of the two arrays. A digitally programmable voltage divider circuit connected in series with the second programmable capacitor array permits the independent programing of notch depth, i.e. without affecting notch width.

Low-passband-sensitivity switched capacitor filters using a parallel connection of two structurally lossless networks

Abstract: The low-sensitivity property of IIR digital filters designed using a parallel connection of two allpass sections has already been demonstrated in the past few years. This property is closely related to the use of a particular type of allpass structures, called structurally lossless networks, which remain allpass regardless of the coefficient quantization. In this paper we provide a general theory for the synthesis of low-passband-sensitivity switched capacitor (SC) filters using a similar technique. the design of stray-insensitive structurally allpass SC sections is emphasized, ensuring the passivity property for the overall filter. Design examples are presented with computer simulations and experimental results to compare the performance of the different proposed structures. Analytical sensitivity calculations are also derived yielding useful formulae for the prediction of the filter sensitivities with respect to capacitor ratios, particularly in the stopband.

Anti-fuse memory device with switched capacitor setting method

Abstract: A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memory cell; a first switch connected between the bit line and a power source; a second switch connected between the power source and the second electrode of the capacitor; and a third switch connected between the second electrode of the capacitor and a ground. A specific memory cell is selected out of the memory cells, and a superposed supply voltage is applied through the capacitor to the anti-fuse of the specific memory by turning on and/or off the first through third switches, so that a storage of information in the memory cell can be performed.

A Single-chip Hearing Aid With One Volt Switched Capacitor Filters

Abstract: An integrated circuit has been designed and fabricated in BiCMOS technology which contains three switchedcapacitor fourth-order filters and one continuous-time fourth-order filter, as well as all other circuitry needed for a modern hearing aid. The circuit operates from a single hearing aid battery and functions down to 1.1 Volt, while the switched-capacitor filters are designed to allow power supplies as low as 1.0 Volt.

Life calculating device for capacitor

Abstract: PURPOSE:To prevent a capacitor from being failed and eliminate failures of a device due to deterioration of the capacitor by calculating the life of capacitor accurately used for the input part of a power converter. CONSTITUTION:An electrolytic capacitor 4 is connected in parallel between a battery 1 and an inverter 2. A control circuit 7 makes a timer 8 to count the operation time of the capacitor 4 and also makes a temperature sensor 6 to detect the temperature inside the capacitor 4. The circuit 7 calculates life consumption time showing how much the operation time equals to, when the capacitor 4 operates at a specified ambient temperature, based on the operation time and inside temperature, and integrates the obtained life consumption time to store the values. When the integrated life consumption time exceeds the specified guaranteed life duration of the capacitor 4 that would be operated at the specified ambient temperature, the circuit 7 judges that the capacitor 4 was short of life, makes a display part 9 to indicate the result, and stops the operation of the inverter 2.

Switched capacitor amplifier circuit operating without serially coupled amplifiers

Abstract: A switched capacitor circuit (10) is responsive to a two phase repetitive clock signal comprised of alternating periods (φ1) and (φ2). The circuit includes a first input branch including a first amplifier (A) for charging a first capacitance (C1) from a first input signal during period (φ2). The circuit further includes a second input branch that includes a second amplifier (B) for charging a second capacitance (CA) from a second input signal during a period (φ1A), and for charging a third capacitance (CB) from the second input signal during a period (φ1B); wherein (φ1A) and (φ1B) alternate in occurrence with one another during successive (φ1) periods. The circuit further includes switches for coupling the first capacitance and the second capacitance to an input of an output amplifier (C) during (φ1B), and for coupling the first capacitance and the third capacitance to the input of the output amplifier during (φ1A). The teaching of the invention provides for the interconnection of several switched capacitor branches without requiring that any two series connected amplifiers settle during the same clock phase.

Time constant detecting circuit and time constant adjusting circuit

Abstract: A time constant detecting circuit incorporated in an LSI detects variations of component values of resistors and capacitors in the LSI by detecting variations of a time constant. A pseudo-resistor is formed by a switched capacitor circuit and at least two switches which are alternately switched on and off in a period T to control a capacitor to be charged and discharged. With the operation of the capacitor having a capacitance C, there is formed a pseudo-resistor having a resistance R p =T/C. A predetermined DC voltage is divided by a series circuit of the pseudo-resistor and an ordinary resistor, and smoothed by a capacitor. The output voltage V out which has been smoothed and appears at the output terminal is uniquely defined by a time constant τ=1/RC, so that the variations of the time constant which are dependent on the resistors and capacitors in the LSI can be detected by a measurement of the output voltage V out .

Switched capacitor networks for focal plane image processing systems

Abstract: The use of switched capacitor (SC) networks as an alternative to large resistor networks for performing computations in VLSI circuits for real-time machine vision and image processing systems is investigated. A mapping can be made from any resistor network to an equivalent SC network that has the same node voltage solution in steady state. However, it takes several switching cycles for a charge to be distributed in the SC network before steady state is reached. Results indicate that SC networks can be used in moderate resolution systems (250*250 pixels) operating at video rate. A chip that implemented several switched capacitor networks for spatial smoothing of images in one dimension was fabricated and tested. The amount of spatial smoothing can be adjusted when the clocking scheme applied to the network is varied. >

Practical aspects of high speed switched-capacitor decimation filter implementation

Abstract: A new approach for monolithic CMOS implementation of the low-pass filter function in analog front-ends for receivers in high speed data communications applications is presented. The approach is based on switched-capacitor transversal filter structures employing parallelism and pipelining to increase throughput. Architectures appropriate for filters with both short and long impulse responses are presented along with necessary hardware requirements. Limitations and the effect of non-idealities on the proposed approach are also discussed. >

SSCNAP: a program for symbolic analysis of switched capacitor circuits

Abstract: The authors present a symbolic switched capacitor (SC) circuit analysis program, called SSCNAP, which was developed on a microcomputer. The program is based on a method that uses numerical algorithms at all stages. Partially or totally symbolic transfer functions, large-change sensitivities, relative sensitivities, and poles and their sensitivities for arbitrary K-phase SC circuits can be obtained using SSCNAP. No topological or duty-cycle constraints have been imposed on the circuits. The discussion is limited to ideal SC circuits that do not contain any resistances. >

Switched capacitor decimator

Abstract: A switched capacitor decimator circuit (20) is shown to be useful in a cellular telephone that operates in accordance with a subaudible signalling protocol. The switched capacitor decimator circuit has an input node for inputting a received signal that includes a subaudible signalling component and an interfering voice component. The switched capacitor decimator circuit further has an output node for outputting a signal having an amplified subaudible signalling component and voice component. The circuit includes an operational amplifier (22) having an input and an output and a characteristic DC offset voltage. A first capacitance (Cint) is switchably coupled, at a rate equal to a first frequency, between the input and the output of the operational amplifier. A second capacitance (Cin) is coupled between the input node and the input of the operational amplifier. A gain (G) of the circuit is given by Ncin/Cint, where n is a ratio of the first frequency to a second, lower frequency. The circuit further includes circuitry (C3, C4) for DC offset compensating the switched capacitor decimator circuit such that the DC offset voltage of the operational amplifier appears at the output node amplified only with a gain of unity.

Tone receiver comprising a switch capacitor zero crossing detector

Abstract: Tone receiver comprising a switched capacitor zero crossing detector (10). The zero crossing detector is arranged for compensating the input offset voltage by causing during a first capacitor switching phase this offset voltage to be present across a capacitor (34) which is connected in parallel with the input of the comparator. At the same time it appears that with this operation any DC voltage component in the input signal can be blocked. With the aid of a voltage step source (46) a voltage step is realised on the input capacitor (34), which step functions as a threshold in the comparator phase. Once the threshold voltage has been exceeded, the comparator is reversed and the processor changes the control of the voltage step source, so that this source produces a threshold voltage of opposite sign. This achieves an effect of hysteresis which counteracts the constant reversing of the comparator.

Programmable PD servo-compensator

Abstract: A programmable PD servo compensator has the transfer function of the combination of a standard PD compensator in tandem with a second order low pass filter. The programmable PD servo compensator consists simply of a biquad filter having a single complex zero and a pair of conjugate complex poles. This servo compensator is comprised of two tandem connected operational amplifiers, each with a capacitor connected output to input across it. The tandem connection is effected by one switched-capacitor resistor between the output of the first amplifier to the input of the second. Another switched-capacitor resistor is connected between the PD compensator input and the input of the first amplifier. Yet another switched capacitor is connected between the PD compensator output and the input of the first amplifier. Additionally, a poles Q-programming circuit branch includes a digitally-programmable capacitor array, and a zero programming circuit branch includes another digitally-programmable capacitor array connected in the filter for determining the S-plane position of the zero and determining the relative gains of the proportional and derivative components of the PD compensator output signal. This is therefore an analog-signal handling servo compensator with digital programmability and having high speed, stability and versatility.

Impedance characterization of GaAs FET switches

Abstract: Since the GaAs FET switch can be regarded as a linear small-signal device in the on and off states, a linear analysis is carried out only of the two states, but taking into account the geometry of electrodes, passivation layers, and depletion regions. The rectangular boundary division method is applied to solve Laplace's equation for the impedance characterization of GaAs FET switches. Equivalent electrical circuits composed of capacitors and resistors are defined for the on state and off state of a FET switch. The capacitances and resistances in the equivalent circuits are estimated and compared with experimentally measured values at 10 GHz. The quality factor of the FET switch, which can be used for estimating insertion loss, is calculated by using the two equivalent series impedances of the FET switch corresponding to the two states. >

Standby circuit for remotely controlled video equipment - incorporates switched-capacitor feed to mains rectifier providing reduced output while load-switching relay is not energised.

Abstract: The load is supplied with mains AC via the contact (5) of a relay (1) whose closure connects two capacitors (3,4) in parallel to the input of the mains rectifier (6). In standby mode the smaller capacitor (3) constitutes a capacitive impedance and the rectifier charges an electrolytic capacitor (7) to a voltage sufficient to supply a microprocessor (2) and infrared detector, but not to hold-in the relay. The larger capacitor (4) compensates for the increased current consumption of the relay winding. USE/ADVANTAGE - Esp. for TV or satellite broadcast receiver or video recorder, substantially reduced power consumption of about 100 mW is achieved with min. circuit complexity.