Showing papers on "Switched capacitor published in 1998"

A switched-current, switched-capacitor temperature sensor in 0.6-/spl mu/m CMOS

Abstract: A temperature-to-digital converter is described which uses a sensor based on the principle of accurately scaled currents in the parasitic substrate p-n-p in a standard fine-line CMOS process. The resulting PTAT /spl delta/V/sub BE/ signal is amplified in an auto-zeroed switched-capacitor circuit, sampled, and converted to a digital output by a low-power 10-bit SAR ADC providing a resolution of 0.25/spl deg/ from -55/spl deg/C to 125/spl deg/C with an error of less than 1/spl deg/. A single adjustment of temperature error is provided for wafer probe. No further calibration is required. A switching bandgap reference circuit will also be described which uses similar techniques to generate an accurate low-noise reference voltage for the ADC. The circuits are part of a multichannel data-acquisition system where other input voltages must also be sampled and measured, and so the speed and power of the ADC is not determined by the temperature sensor alone. For continuous operation, the supply current is 1 mA, but a low-power mode is provided where the part is normally in shut down and only powers up when required. In this mode, the average power supply current at 10 conversions/s is 0.3 /spl mu/A. The supply voltage is 2.7-5.5 V.

Switched-capacitor inverter with high power density and enhanced regulation capability

Abstract: A DC-AC inverter containing no inductors or transformers is presented. The role of the magnetic devices is played by a switched-capacitor (SC) circuit, formed by two subcircuits. Each SC-subcircuit contains 15 basic cells, each one formed by one capacitor, two MOSFETs and two diodes. The sinusoidal output waveform is realized in a staircase, formed by 64 steps. To achieve each step, the inverter operates like a step-up DC-DC converter: by using a certain number of SC-cells, the input voltage is boosted to the voltage required by the step in consideration. Each step is implemented in a large number of switching cycles. In each cycle, the inverter goes through four phases; according to a designed switching sequence, some of the capacitors of the SC-cells involved in the respective step are in a charging process from line, while the others are in a discharging process to the load. The phases 2 and 4 have a regulation role only. A duty cycle control is used. A Fourier analysis evidences the clean AC output waveform. The inverter exhibits low weight, high power density, and enhanced regulation for large changes in line and load.

New generation of switched capacitor converters

Abstract: This paper presents a new generation of switched capacitor power converters. These new circuits use a reduced number of switches. The new family consists of three circuit topologies: double; inverting; and half the input voltage. All the switching devices are zero-current switching and hence the converter can operate at high switching frequency. The high switching current has also been reduced.

A 15-b resolution 2-MHz Nyquist rate /spl Delta//spl Sigma/ ADC in a 1-/spl mu/m CMOS technology

Abstract: A high-resolution high-speed fourth-order cascaded /spl Delta//spl Sigma/ analog-to-digital converter, based on a 2-1-1 topology, is presented. The converter is implemented with fully differential switched capacitor circuits in a standard 1-/spl mu/m CMOS technology. The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage.

Method for fabricating a shielded multilevel integrated circuit capacitor

Abstract: A multilevel capacitor structure compatible with CMOS processing for use in switched capacitor circuits is disclosed. The capacitor structure has an associated parasitic capacitor which is placed in such a way so as to minimize the impact on the performance of a the switched capacitor circuit. The parasitic capacitor is formed between a first plate of the shielded capacitor and a diffusion well within a substrate. The diffusion well is connected to a quiet voltage reference source to isolate the shielded capacitor from noise present on the substrate. The shielded capacitor has a first plate that is fabricated from a first conductive material such as polycrystalline silicon or polycide, a second plate fabricated from a second conductive material such as a first level of metal on an integrated circuit, and a third capacitor plate fabricated from a second level of metal of an integrated circuit. The first plate and the third plate are connected to give a total capacitance given by the sum of capacitances between the first plate and second plate and between the second plate and third plate.

Switched-capacitor sigma-delta analog-to-digital converter with input voltage overload protection

Abstract: A sigma-delta analog-to-digital converter includes an integrator having an input and an output and an integrator capacitor connected between the input and output. A switched-capacitor input circuit includes at least one input capacitor, an input sampling switching circuit and an input delivery switching circuit. The input sampling switching circuit includes at least one input sampling switch operable to connect the input capacitor to be charged by an input voltage at a sampling rate. The input delivery switching circuit includes at least one input delivery switch operable to connect the input capacitor to transfer charge to the integrator capacitor at a first transfer rate. A switched-capacitor feedback circuit is connected in a feedback path between the input and output of the integrator. The feedback circuit includes at least one feedback capacitor, a feedback sampling switching circuit and a feedback delivery switching circuit. The feedback sampling switching circuit includes at least one feedback sampling switch operable to connect the feedback capacitor to be charged by a feedback reference voltage at the sampling rate. The feedback delivery switching circuit includes at least one feedback delivery switch operable to connect the feedback capacitor to transfer charge to the integrator capacitor at a second transfer rate. The second transfer rate is a predetermined factor greater than the first transfer rate such that the sampled feedback reference voltage charge is transferred to the integrator capacitor at a greater rate than the transfer of the sampled input voltage charge to prevent modulator instability due to an input overload condition.

Apparatus and method for resetting delta-sigma modulator state variables using feedback impedance

Abstract: A technique for resetting state variables of a delta-sigma modulator of an analog-to-digital converter. A switched capacitor impedance is placed in the reset feedback path of an integrator to ensure that the integrator tracks to the proper reset voltage, when reset is initiated in a third-order or higher delta-sigma modulator.

A high-accuracy, high-speed signal processing circuit of differential-capacitance transducers

Abstract: For high-accuracy signal processing of differential-capacitance transducers, an interface circuitry is developed based on a relaxation oscillator. The interface consists of an integrator, a differentiator, and a comparator, and it uses two capacitors of the transducer-one for the integration and the other for the differentiation. This configuration allows the ratiometric operation in the amplitude domain and provides a square wave whose amplitude is proportional to the ratio of the capacitance difference between the two transducer capacitors to their sum. A circuit analysis shows that the interface can detect the capacitance change as small as 0.1% of the total capacitance in 10 /spl mu/s. Experimental results are also given to confirm the analysis.

Reference voltage circuitry for use in switched-capacitor applications

Abstract: Circuitry for selectively sampling a reference voltage with a capacitor 403 includes a first switch 505a for selectively coupling capacitor 403 to a source of a first reference signal during a first operating phase and a second switch 505b for selectively coupling capacitor 403 to a source of a second reference signal during a second operating phase.

A Novel Switched-Capacitor Based Field-Programmable Analog Array Architecture

Abstract: A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).

An Eight-order Bandpass /spl delta/ /spl sigma/l Modulator For A/D Conversion In Digital Radio

Abstract: This paper examines the design and implementation of an eighth-order bandpass delta-sigma modulator. The design process is investigated from the signal flow graph level, through to the details of the switched capacitor implementation and layout considerations. Simulation results, highlighting the effects of process variation, are provided and the experimental performance of the modulator described. The modulator is implemented in a 0.8-/spl mu/m BiCMOS process and occupies an active area of 1.7 mm/sup 2/. Operating from /spl plusmn/2.5-V supplies, the fabricated prototype exhibits stable behaviour and achieves a dynamic range of 67 dB over a 200-kHz bandwidth centered at the commonly used intermediate frequency of 10.7 MHz. This paper, therefore, demonstrates the viability of high-order single-bit bandpass delta-sigma modulation.

Method and device for analogue to digital conversion

Abstract: According to an embodiment of the invention, a parallel SC ADC (switched capacitor analogue-to-digital converter) is provided, comprising a passive sampling technique controlled by a global clock phase (ζ) to reduce the influence of the sampling phase skew. Since it does not require operational amplifiers for sampling, it is very suitable for high speed applications, and yet it can reduce the sampling-phase-skew-related distortion by 20-40dB in a high speed, parallel SC ADC.

Five-level switched-capacitor DAC, method of operation thereof and sigma-delta converter employing the same

Abstract: A digital-to-analog converter (DAC) and a method of converting digital numbers to analog equivalents. In one embodiment, the DAC includes: (1) a data decoder that receives a digital number and an input clock signal and develops therefrom SIGN and M control signals and complementary φ 1 and φ 2 clock signals and (2) a conversion circuit, coupled to the data decoder and including first and second operational amplifiers (op amps), a switching circuit and sampling and integrating capacitors, the switching circuit coupling positive and negative reference voltages to the sampling capacitors as a function of states of the SIGN and M control signals and adjusting feedback loops associated with the first and second op amps as a function of states of the φ 1 and φ 2 clock signals, the first and second op amps generating a voltage difference at outputs thereof representing an analog equivalent of the digital number.

Phase detector using switched capacitors

Abstract: A phase detector operating in a low voltage environment and providing a substantially constant integral voltage over variations in temperature, supply voltage and process parameters. The quadrature phase detector includes an equalizer, a switching unit, a sampler and comparator unit and a bias generator. The bias generator includes a switched capacitor structure which produces a bias current which tracks fluctuations in capacitance values due to temperature, supply voltage and process variations. The errors introduced due to fluctuations in bias current and capacitance are thus minimized.

MOS sample and hold circuit

Abstract: A MOS track-and-hold circuit incorporating cancellation of error due to switch feedthrough is described. To eliminate the channel charge feedthrough due to oxide capacitance, a switched capacitor source (22) is connected to be charged to a voltage V1 during the "hold" phase and between the input node (12) and the switch gate (17) to provide a voltage V1-Vin during the "track" phase. A dummy transistor (26) biased in an "off" condition has its drain connected to the holding capacitor (15) and its gate switched between ground and the output terminal (Vout which tracks Vin) to also cancel the feedthrough from the gate-drain overlap capacitance and any gate-drain parasitic capacitance.

Liquid crystal driving circuit for driving a liquid crystal display panel

Abstract: A liquid crystal driving circuit including a switched capacitor circuit 15 having a pair of operational amplifiers AMP1 and AMP2 having different reference voltages, and an output selection circuit 16 for switch-controlling the respective outputs of the operational amplifiers AMP1 and AMP2 to output at a pair of output terminals. Positive and negative output voltages which are in positive and negative amplitude relationship with each other with a half of the liquid crystal driving voltage or the voltage of the common electrode of the liquid crystal display device as a reference voltage are alternately output from the pair of output terminals of the output selection circuit 16 to the common electrode of the liquid crystal display device, thereby performing an alternating current driving operation of the liquid crystal display device in accordance with video data.

An active charge-cancellation system for switched-capacitor sensor interface circuits

Abstract: Interface circuits determine the performance of microsensors in diverse automotive, medical, and process-control applications. Microsensor systems for acceleration, rotation, pressure, and other signals most typically rely on capacitive displacement measurement in microstructures. Displacement sensitivity requirements are typically 0.1 pm with sensor capacitor values of 100 fF or less. Conventional architectures for capacitive displacement measurement have required bias control with either large value off-chip or large-area integrated resistive circuit components. Switched-capacitor measurement methods may provide a fully integrated solution with compact geometry but have been limited by severe charge injection error signals. The active charge cancellation system (ACCS), reported here, provides the first direct compensation of switched-capacitor charge-injection error at the measurement system input. The ACCS, implemented in a 0.8-/spl mu/m digital CMOS technology, uses a novel feedback network to directly cancel charge injection and reduce error by over two orders of magnitude without need for component matching.

DPAD2—A Field Programmable Analog Array

Abstract: DPAD2 is a Field Programmable Analog Array (FPAA) based on CMOS switched capacitor technology. This paper describes the major design decisions that went into creating DPAD2 with respect to the ultimate goal of the work, being a mixed signal field programmable silicon solution. Two major compromises exist in the design of an FPAA, one between flexibility and performance, the other between functionality and die size; DPAD2 overcomes the first with a novel field programmable hierarchic routing scheme and the second by careful analysis of many disparate designs to arrive at a best compromise solution. Results from prototype silicon are presented where a single analog cell is reconfigured to perform a number of different analog signal processing functions. Bandwidth of the DPAD2 device is 500 kHz and the SNR is typically 60 dB, although both are application dependent. Introduction of the FPAA now enables a designer to have working silicon within one day, by a simple configuration of the silicon chip via a PC parallel interface. Software libraries of analog circuits are provided and allow very rapid creation of large and complex analog circuits.

Stimulus system with controllable switched capacitor output stage

Abstract: There is provided an output stage for a battery powered implantable device, such as a cardiac pacemaker, for generating biphasic or triphasic pulses, each pulse having at least a prestimulus or poststimulus pulse of a first polarity, and a stimulus pulse of opposite polarity. The output stage provides for charging of a small sized pacing capacitor from the battery through a high rate charge pump only during delivery of a prestim or poststim pulse, and for discharging the pacing capacitor during the stimulus portion of the overall pulse. A fast or high rate capacitive charge pump is used with a controllable high rate clock signal, adjustment of the clock signal being used for controlling the charging rate during the prestim or poststim pulses, thereby allowing for tuning of the parameters of the prestim or poststim pulse portions. The charge pump is enabled only during such charging pulse durations, thereby eliminating the need for a large holding capacitor, and enabling an output stage with a significantly reduced capacitor requirement.

CMOS switched-op amp based sample-and-hold circuit

Abstract: This paper presents a sample-and-hold design that is based on a switched-op amp. By using a switched-opamp topology charge injection errors are greatly reduced by turning off the transistors in saturation instead of triode region. A pseudo-differential topology is used to cancel the remaining signal independent clock feedthrough error. Switched op amps with differential pairs in both weak inversion and strong inversion are designed. Detailed simulation and measurement results of a switched-opamp based sample and hold circuit is used to show its performance superiority over traditional switched capacitor topologies.

Capacitor mismatch compensation for the quasi-passive-switched-capacitor DAC

Abstract: A method to eliminate the effect of capacitor mismatch for a switched-capacitor DAC is described. The method consists of two elements. The first element is the use of a compensating switching algorithm, which can eliminate the effect of capacitor mismatch only for some digital input values. The second element is that each digital word is written as the sum of two other words for which the capacitor mismatch can be eliminated. These words are converted and the corresponding voltages are summed.

Closed-loop switched capacitor network power supply

Abstract: A closed-loop switched capacitor power supply converts a supply voltage into an output voltage that rapidly approaches a set-point voltage by using a variable frequency source, a switched capacitor network and a feedback control circuit. The variable frequency source provides the switched capacitor network with a control voltage having a control frequency that affects the impedance of the switched capacitor network. The switched capacitor network comprises one or more network sections, each one having a grounded capacitor with the other terminal coupled to a supply voltage through a first switch and coupled to the load through a second switch. The first and second switches work in a complementary manner, such that when the first switch is closed the capacitor is charged by the supply voltage, and when the second switch is closed the capacitor discharges into the output of the switched capacitor network. The feedback control circuit is coupled to the output of the switched capacitor network and uses a proportional integral/derivative compensator to regulate the control frequency of the variable frequency source in accordance with the difference between the output voltage and the set-point value. In this way, the output voltage of the power supply can be controlled by varying the frequency of the control voltage of the variable frequency source. Embodiments with additional capacitor networks are advantageous as output ripple is reduced and the overall energy efficiency of the circuit is increased. The power supply is also capable of measuring the power consumption of the load with high accuracy.

Soft-switched built-in active snubber circuit

Abstract: A snubber circuit with two switches which are switched together. The two switches form a pair of active networks with complementary diode locations, and a capacitor is connected to provide a path for transient current through both diodes. The two switches are preferably switched simultaneously to minimize conduction losses. When Switches S1 and S2 are turned off, the voltage through across capacitor Cs is nearly zero. Turning off S1 and S2 causes current flowing through S1 and S2 to be diverted through D1, Cs, and D2. Therefore, the voltage across S1 and S2 is a very low value and consequently, the turn-off losses are low. Alternatively, at the time when S1 and S2 are turned on, the peak current through S1 and S2 is equal to the boost inductor current. Therefore switching losses are minimized and the converter can operate at higher frequencies.

Sigma delta modulator with automatic saturation detection and recovery

Abstract: In the present invention is described a forward feed sigma delta modulator of higher order having automatic saturation detection and recovery. The modulator is separated into two parts which are connected together when there is no saturation, and disconnected when saturation is detected and recovery takes place. The first part contains an integrator and input output circuitry to allow continuous operation of the modulator. The second part contains additional integrators to provider for a higher order modulator and the saturation detector. The modulator can be constructed of single ended or differential switched capacitor technology, and there is a digital saturation detection scheme.

Capacitive level sensor for measuring filling level of liquid in container

Abstract: The sensor has measurement electrodes (308,310;600) each made up of a first capacitor sensor element (C1) and a second capacitive sensor element (C2). A switched capacitor measurement circuit is connected to the two capacitive elements of each measurement element to determine their capacitance from which a signal is generated indicating the filling level. The measurement electrodes are located on opposite sections of the sides (312,314) of the container (300) holding the liquid. The measurement electrodes can be in the form of a ribbon cable with the capacitive sensor elements formed by conductor pairs

A Switched Capacitor Approach to Field-Programmable Analog Array (FPAA) Design

Abstract: We present a voltage mode switched-capacitor Field Programmable Analog Array (FPAA) to be used to implement various analog circuits The FPAA consists of uniform configurable analog blocks (CABs) allowing implementation of different functions Each CAB consists of two back-to-back connected inverting and non-inverting strays-insensitive switched-capacitor integrators The interconnection between CABs is implemented by switched and unswitched capacitor networks The internal structure of CABs and the interconnection between different CABs are configured by user-programmable digital control signals The functionality of the FPAA is demonstrated through embedding of different types of filters, programmable amplifiers, biquads, modulators and signal generators along with simulation results

Input sampling structure for delta-sigma modulator

Abstract: A signal processing circuit includes a main input sampling structure with an integrator operational amplifier and input lines including a switched capacitor. The input lines have switched connections to input signal lines and reference signal lines. A replica sampling structure is used in combination with the main input sampling structure to eliminate or reduce signal-dependent current that is drawn from the input signal line and the reference signal line. The replica sampler includes buffered input lines and switched capacitor of the input sampling structure but the capacitors have switched connections to the reference signal lines such that the connections have opposite polarity to the connections of the reference signal line to the input sampling structure. The replica sampler eliminates or reduces signal-dependent current from the reference signal lines. Buffering of the input lines in the replica sampler eliminates or reduces the signal-dependent current drawn from the input signal lines. The structure efficiently allows the use of a smaller capacitance for the same performance.

Binary controlled static VAr compensator, based on electronically switched capacitors

Abstract: A binary control strategy for reactive power compensation, based on a chain of branches using unidirectional power switches is presented. This strategy allows, with an adequate number of compensating branches, a fine and precise control of reactive power in electric systems. The amount of reactive power is evaluated by storing the value of instantaneous line current during the "zero-crossing" of the mains voltage. Other characteristics of this control strategy are: (1) it does not generate harmonics; (2) it can compensate reactive power in an almost continuous form; and (3) inrush problems during connection and/or disconnection are avoided. The paper explains the control strategy proposed, the way it works and some results obtained under operation.

Generalized procedure for the calibration of switched capacitor gain stages

Abstract: Within the field of integrated circuits used in amplifiers, a structure and improved method for calibrating a switched capacitor gain stage wherein the time required to self-calibrate a switched capacitor gain stage and the associated structure are reduced. The invention utilizes only a single calibration step which is performed while the output of the amplifier being calibrated is monitored. Instead of utilizing a plurality of capacitors C a1 --C an each in parallel with groups of trim capacitors C T , a single capacitor C a is used and connected to switches S 1a1 and S 1b1 . Further, instead of a group of trim capacitors C T being connected in parallel with the capacitor to be trimmed, each of plurality of trim capacitors C T1 -C TN is connected between the input to the operational amplifier and a respective corresponding switch S 1a2 -S 1aN to the input reference voltage node V b0 . As well, switches S 1b2 -S 1bn connect the respective junctions between the trim capacitors C T1 -C TN to ground.

Switched capacitor circuit and method for reducing sampling noise

Abstract: A switched capacitor circuit (60) reduces sampling noise by oversampling an input signal in space domain. The switched capacitor circuit (60) includes four sampling capacitors (72, 74, 76, 78) serially coupled together via five integrating switches (71, 73, 75, 77, 79). Each clock cycle of the oversampling process has a sampling phase and an integrating phase. In the sampling phase, the integrating switches (71, 73, 75, 77, 79) are nonconductive and the sampling capacitors (72, 74, 76, 78) sample the input signal through eight sampling switches (81, 82, 83, 84, 85, 86, 87, 88). In the integrating phase, the charge stored in the sampling capacitors (72, 74, 76, 78) is transferred to an integrator (90).