Showing papers on "VHDL published in 2000"

Stream-oriented FPGA computing in the Streams-C high level language

Abstract: Stream oriented processing is an important methodology used in FPGA-based parallel processing. Characteristics of stream-oriented computing include high-data-rate flow of one or more data sources; fixed size, small stream payload (one byte to one word); compute-intensive operations, usually low precision fixed point, on the data stream; access to small local memories holding coefficients and other constants; and occasional synchronization between computational phases. We describe language constructs, compiler technology, and hardware/software libraries embodying the Streams-C system which has been developed to support stream-oriented computation on FPGA-based parallel computers. The language is implemented as a small set of library functions callable from a C language program. The Streams-C compiler synthesizes hardware circuits for multiple FPGAs as well as a multi-threaded software program for the control processor. Our system includes a functional simulation environment based on POSIX threads, allowing the programmer to simulate the collection of parallel processes and their communication at the functional level. Finally we present an application written both in Streams-C and hand-coded in VHDL. Compared to the hand-crafted design, the Streams-C-generated circuit takes 3x the area and runs at 1/2 the clock rate. In terms of time to market, the hand-done design took a month to develop by an experienced hardware developer. The Streams-C design rook a couple of days, for a productivity increase of 10x.

An implementation of fuzzy logic controller on the reconfigurable FPGA system

Abstract: This paper concerns an implementation of a fuzzy logic controller (FLC) on a reconfigurable field-programmable gate array (FPGA) system. In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually on the FLC automatic design and implementation system, which is an integrated development environment for performing many subtasks such as automatic VHSIC hardware description language description, FPGA synthesis, optimization, placement and routing, and downloading. Each implemented module forms a downloadable hardware object that is ready to configure the FPGA chip. Then, the FPGA chip is consequently reconfigured with one module at a time by using the run-time reconfiguration method. This implementation method is effective when a single FPGA chip cannot fit the FLC due to the limited size of its constituent cells. We test the proposed implementation method by building the FLC for the truck backer-upper control on VCC Corporation's EVC-1 reconfigurable FPGA board directly.

High-level synthesis of nonprogrammable hardware accelerators

Abstract: The PICO-N system automatically synthesizes embedded nonprogrammable accelerators to be used as co-processors for functions expressed as loop nests in C. The output is synthesizable VHDL that defines the accelerator at the register transfer level (RTL). The system generates a synchronous array of customized VLIW (very-long instruction word) processors, their controller local memory, and interfaces. The system also modifies the user's application software to make use of the generated accelerator. The user indicates the throughput to be achieved by specifying the number of processors and their initiation interval. In experimental comparisons, PICO-N designs are slightly more costly than hand-designed accelerators with the same performance.

Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor

Abstract: Using SEUTool (a synthesized VHDL based simulator of single-event fault propagation in combinational circuitry), we have performed a single-event study on a custom-designed CMOS AM2901, a 4-bit bit-slice processor. Analysis shows interesting general trends for single-event upset effects in complex combinational/sequential circuits.

Digital system design with VHDL

Abstract: From the Publisher: Digital System Design with VHDL is intended both for students on Digital Design courses and practitioners who would like to integrate digital design and VHDL synthesis in the workplace Its unique approach combines the principles of digital design with a guide to the use of VHDL Synthesis issues are discussed and practical guidelines are provided for improving simulation accuracy and performance Features: a practical perspective is obtained by the inclusion of real-life examples an emphasis on software engineering practices encourages clear coding and adequate documentation of the process demonstrates the effects of particular coding styles on synthesis and simulation efficiency covers the major VHDL standards includes an appendix with examples in Verilog

Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation

Abstract: The paper describes the implementation of a systolic array for a multilayer perceptron on a Virtex XCV400 FPGA with a hardware-friendly learning algorithm. A pipelined adaptation of the on-line backpropagation algorithm is shown. Parallelism is better exploited because both forward and backward phases can be performed simultaneously. We can implement very large interconnection layers by using large Xilinx devices with embedded memories alongside the projection used in the systolic architecture. These physical and architectural features --- together with the combination of FPGA reconfiguration properties with a design flow based on generic VHDL --- create an easy, flexible, and fast method of designing a complete ANN on a single FPGA. The result offers a high degree of parallelism and fast performance.

Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms.

Abstract: The National Security Agency (NSA) is providing hardware simulation support and performance measurements to aid NIST in their selection of the AES algorithm. Although much of the Round 1 analysis focused on software, much more attention will be directed towards hardware implementation issues in the Round 2 analysis. As NIST has stated, a common set of assumptions will be essential in comparing the hardware efficiency of the finalists. This paper presents a technical overview of the methods and approaches used to analyze the Round 2 candidate algorithms (MARS, RC6, RIJNDAEL, SERPENT and TWOFISH) in CMOS-based hardware. Both design procedures and architectures will be presented to provide an overview of each of the algorithms and the methods used. To cover a wide range of potential hardware applications, two distinct architectures will be targeted for comparison, specifically a medium speed, small area iterated version and a high speed, large area pipelined version. The standard design approach will consist of creating hardware models using VHDL and an underlying library of cryptographic components to completely describe each algorithm. Once generated, the model can be verified for correctness through simulation and comparison to test vectors, and synthesized to a common CMOS hardware library for performance analysis. Hardware performance data will be collected for a variety of design constraints for each of the algorithms to ensure a wide range of measured data. A summary report of the findings will be presented to demonstrate algorithm performance across a wide range of metrics, such as speed, area, and throughput. This report will provide a common baseline of information, which will enable NIST and the community to compare the hardware performance of the algorithms relative to one another.

Fault injection in VHDL descriptions and emulation

Abstract: Analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of faults. It is proposed to carry out such an analysis using fault injections in RT-level VHDL descriptions and hardware prototyping of the circuit under design. Injection of erroneous transitions is automated and results are presented.

Automatic code generation for integrated circuit design

Abstract: An integrated circuit is designed by interconnecting pre-designed data-driven cores (intellectual property, functional blocks). Hardware description language (e.g. Verilog or VHDL) and software language (e.g. C or C++) code for interconnecting the cores is automatically generated by software tools from a central circuit specification. The central specification recites pre-designed hardware cores (intellectual property) and the interconnections between the cores. HDL and software language test benches, and timing constraints are also automatically generated from the central specification. The automatic generation of code simplifies the interconnection of pre-existing cores for the design of complex integrated circuits.

Vhdl Design Representation and Synthesis

Abstract: Preface. 1. Structured Design Concepts. The Abstraction Hierarchy. Textual vs Pictorial Representations. Types of Behavioral Descriptions. Design Process. Structural Design Decomposition. The Digital Design Space. 2. Design Tools. CAD Tool Taxonomy. Schematic Editors. Simulators. The Simulation System. Simulation Aids. Applications of Simulation. Synthesis Tools. 3. Basic Features of VHDL. Major Language Constructs. 3. Lexical Description. Character Set. VHDL Source File. Data Types. Data Objects. Language Statements. Advanced Features of VHDL. The Formal Nature of VHDL. VHDL 93. Summary. 4. Basic VHDL Modeling Techniques. Modeling Delay in VHDL. The VHDL Scheduling Algorithm. Modeling Combinational and Sequential Logic. Logic Primitives. 5. Algorithmic Level Design. General Algorithmic Model Development in the Behavioral Domain. Representation of System Interconnections. Algorithmic Modeling of Systems. 6. Register Level Design. Transition from Algorithmic to Data Flow Descriptions. Timing Analysis. Control Unit Design. Ultimate RISC Machine. 7. Gate Level and ASIC Library Modeling. Accurate Gate Level Modeling. Error Checking. Multivalued Logic for Gate Level Modeling. Configuration Declarations for Gate Level Models. Modeling Races and Hazards. Approaches to Delay Control. 8. HDL-Based Design Techniques. Design of Combinational Logic Circuits. Design of Sequential Logic Circuits. Design of Microprogrammed Control Units. 9. ASICs and the ASIC Design Process. What is an ASIC? ASIC Circuit Technology. Types of ASICs. The ASIC Design Process. FPGA Synthesis. 10. Modeling for Synthesis. Behavioral Model Development. The Semantics of Simulation and Synthesis. Modeling Sequential Behavior. Modeling Combinational Circuits for Synthesis. Inferred Latches and Don't Cares. Tristate Circuits. Shared Resources. Flattening and Structuring. Effect of Modeling Style On Circuit Complexity. 11. Integration of VHDL into a Top-Down Design Methodology. Top-Down Design Methodology. Sobel Edge Detection Algorithm. System Requirements Level. System Definition Level. Architecture Design. Detailed Design at the RTL Level. Detailed Design at the Gate Level. 12. Synthesis Algorithms for Design Automation. Benefits of Algorithmic Synthesis. Algorithmic Synthesis Tasks. Scheduling Techniques. Allocation Techniques. State of the Art in High-Level Synthesis. Automated Synthesis of VHDL Constructs. Index. References. About the Authors. Index.

Introductory VHDL: From Simulation to Synthesis

Abstract: From the Publisher: This book focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises, and tutorials are provided for the use of the new integrated design environments from Xilinx-which is available with the book. For engineers interested in Digital Design Laboratory, Digital Design, Advanced Digital Design, and Advanced Digital Logic

New techniques for accelerating fault injection in VHDL descriptions

Abstract: Simulation-based fault injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. However, the large CPU time required to perform VHDL simulations often represents a major drawback stemming from the adoption of this method. This paper presents some techniques for reducing the time to perform the fault injection experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, and for removing faults as soon as their behaviour is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical fault injection campaign by a factor ranging from 51% to 96%.

HML, a novel hardware description language and its translation to VHDL

Abstract: We present hardware ML (HML), an innovative hardware description language (HDL) based on the functional programming language SML. Features of HML not found in other HDL's include polymorphic types and advanced type checking and type inference techniques. We have implemented an HML type checker and a translator for automatically generating VHDL from HML descriptions. We generate a synthesizable subset of VHDL and automatically infer types and interfaces. This paper gives an overview of HML and discusses the translation from HML to VHDL and the type inference process.

Efficient hardware controller synthesis for synchronous dataflow graph in system level design

Abstract: This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow graph represents a hardware library module that contains a synthesizable VHDL code. Our proposed technique automatically synthesizes a clever control structure, cascaded counter controller, that supports asynchronous interaction with outside modules while efficiently implementing the synchronous dataflow semantics of the graph at the same time. Through comparison with previous work with some examples, the novelty of the proposed technique is demonstrated.

Hardware implementation of the improved WEP and RC4 encryption algorithms for wireless terminals

Abstract: This paper presents hardware implementations for Improved Wired Equivalent Privacy (IWEP) and RC4 ("Ron's Cipher #4") encryption algorithms. IWEP is a block algorithm providing light-strength encryption. The algorithm has been designed for a new Wireless Local Area Network (WLAN), called TUTWLAN (Tampere University of Technology Wireless Local Area Network). On the contrary RC4, developed by RSA Data Security, Inc., is a powerful stream algorithm used in many commercial products. It is also utilized in the Wired Equivalent Privacy (WEP) standard algorithm for WLANs. The objective of this work has been to study the suitability of hardware implementation for these previously software-implemented ciphers. Hardware is needed to replace software especially in wireless multimedia terminals, in which real-time data processing and limited on-chip memory sizes are key elements. The implementations are made in Very highspeed integrated circuit Hardware Description Language (VHDL) on Xilinx Field Programmable Gate Array (FPGA) chips.

Design of VHDL-based totally self-checking finite-state machine and data-path descriptions

Abstract: This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifications. The control part of the system is designed to be self-checking by adopting a state assignment providing a constant Hamming distance between each pair of binary codes. The design of the data path is based on both classical methodologies (e.g., parity, Berger code) and ad hoc strategies (e.g., multiplexer cycle) suited for the specific circuit structure. Self-checking properties and costs are evaluated on a set of benchmark FSM's and on a number of VHDL circuits.

FPGA-based Internet protocol firewall chip

Abstract: We present the design of a firewall for IP networks using a field-programmable gate array (FPGA). The FPGA implements, in hardware, the accept or deny rules of the firewall. A hardware-based firewall offers the advantages of speed over a software firewall, in addition to direct interfacing with network devices, such as an Ethernet or a serial line transceiver. This paper shows how the rules are translated to VHDL and then implemented in hardware, and how the hardware is utilized to filter network traffic in a packet-by-packet fashion, or based on connection information, with a speed of more than 500,000 packets per second.

Realization of the Round 2 AES Candidates using Altera FPGA

Abstract: This paper presents an evaluation of five Round 2 Advanced Encryption Standard (AES) candidates from the viewpoint of their realization in a FPGA. After the analysis of the general characteristics of the algorithms a general cipher structure is defined. Using this structure, the suitability of available FPGA families is evaluated. Finally, three algorithms – RIJNDAEL [5], SERPENT [6] and TWOFISH [7] are realized in VHDL and implemented in the selected FPGA family.

An RT-level fault model with high gate level correlation

Abstract: With the advent of new RT-level design and test flows, new tools are needed to migrate at the RT-level the activities of fault simulation testability analysis, and test pattern generation. This paper focuses on fault simulation at the RT-level, and aims at exploiting the capabilities of VHDL simulators to compute faulty responses. The simulator was implemented as a phototypical tool, and experimental results show that simulation of a faulty circuit is no more costly than simulation of the original circuit. The reliability of the fault coverage figures computed at the RT-level is increased thanks to an analysis of inherent VHDL redundancies, and by foreseeing classical synthesis optimizations. A set of "rules" is used to compute a fault list that exhibits good correlation with stuck-at faults.

Design of real-time image enhancement preprocessor for CMOS image sensor

Abstract: This paper presents a design of the real-time digital image enhancement preprocessor for a CMOS image sensor. The CMOS image sensor offers various advantages while it provides lower-quality images than the CCD does. In order to compensate for the physical limitation of the CMOS sensor, a spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19 K logic gates, which is suitable for a low-cost one-chip PC camera. The test system was implemented on a FPGA chip in real-time mode, and performed successfully.

Digital Design with CPLD Applications and VHDL

Abstract: From the Publisher: Digital Design with CPLD Applications and VHDL uses programmable logic as the primary vehicle for instructing readers in the principles of digital design. More specifically, emphasis is on Complex Programmable Logic Devices (CPLDs) and the software tools used for their programming, with a decided shift away from fixed-function SSI and MSI devices. Immediately following discussion of digital fundamentals, Digital Design with CPLD Applications and VHDL introduces its readers to Complex Programmable Logic Devices.

Compiling and optimizing image processing algorithms for FPGAs

Abstract: This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient compilation to FPGAs. It then describes the compilation process, in which SA-C algorithms are translated into non-recursive data flow graphs, which in turn are translated into VHDL. Finally, it presents performance numbers for some well-known image processing routines, written in SAC and automatically compiled to an Annapolis Microsystems WildForce board with Xilinx 4036XL FPGAs.

FPGA-based coprocessor for text string extraction

Abstract: In document understanding, one of the early stages involves extracting text strings from a scanned image of the document. Often, the text is printed on a repetitive background of design patterns for visual effects. For recognition purposes, the text strings need to be extracted eliminating the background. Image morphology based algorithms have been proposed for this purpose. However, image morphology operations are compute intensive. We describe the design and synthesis of a high-performance coprocessor to meet the compute load. The algorithm has been synthesized for Splash 2, an attached processor on Sun hosts. The Xilinx Field-Programmable Gate Array (FPGA) based PEs are programmed using VHDL behavioral modeling. The design can run at near-ASIC speeds of /spl ap/22 MHz clock rate with effective timing of 3 milliseconds per 128/spl times/128 image frame and 3/spl times/3 structuring element. Compared with a SPARC station 20 timings of 1.5 sees, the present implementation has a speed advantage of the order of 500 times.

Designing a Radiation Hardened 8051-Like Micro-Controller

Abstract: This paper presents a prototype of a hardened version of the 8051 micro-controller, able to assure reliable operation in the presence of bit flips caused by radiation. Aiming at avoiding such faults in the 8051 micro-controller, Hamming code protection was used in its SRAM memory and registers. This paper shows implementation details of this technique in the micro-controller VHDL description and the impact on the device area.

A VHDL error simulator for functional test generation

Abstract: This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. All components of the simulation environment are automatically built starting from the VHDL specification of the description under test. The effectiveness of the simulator has been measured by using a random functional test generator. Functional test patterns produce, on some benchmarks, a higher gate-level fault coverage than the fault coverage achieved by a very efficient gate-level test pattern generator. Moreover, functional test generation requires a fraction of the time necessary to generate test at the gate level. This is due to the possibility of effectively exploring the test patterns space since error simulation is directly performed at the VHDL level.

20 GFLOPS QR processor on a Xilinx Virtex-E FPGA

Abstract: Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In highsample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable GateArray (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimised to the target application to minimise component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterised implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

The VHDL Reference: A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS

Abstract: From the Publisher: The VHDL Reference: The essential guide for students and professionals working in computer hardware design and synthesis. The definitive guide to VHDL, this book combines a comprehensive reference of the VHDL syntax with tutorial and workshop materials that guide the reader through the principles of digital hardware design. The Authors describe the concept of VHDL and VHDL-AMS for modelling and synthesis and explain how VHDL can be used for the design of digital systems. The CD-ROM features workshop and reference material to familiarise beginners with the use of VHDL for simulation and for synthesis. In-depth examples of VHDL construct are explained in compact and easy to follow form providing immediate help and answers to specific problems. Features include: * Accompanying CD-ROM version of the VHDL Reference including demonstration tools and workshop material covering language aspects for digital systems.* Modelling tutorial featuring VHDL-AMS, the new standard for modelling and simulating mixed signal micro systems. Real-life examples enable the reader to test their knowledge and clarify their understanding of the concepts.* Design workshop format taking the reader through an entire circuit design using an actual design problem, allowing beginners to put their VHDL skills into practice.* A user friendly reference section providing in depth coverage of the VHDL language for digital systems.* Includes tools for editing VHDL source files, simulating and synthesising VHDL models. The VHDL Reference is a highly accessible single source reference to the industry standard language for computer-aided electronic system design. It is not only an essential guide forundergraduate and postgraduate students in electrical engineering but also an indispensable aid to researchers and hardware designers and teachers using VHDL and logic synthesis.

VHDL Coding and Logic Synthesis with Synopsys

Abstract: From the Publisher: This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas.Synopsys is the dominant computer-aided circuit design program in the world. All of the major circuit manufacturers and ASIC design firms use Synopsys. In addition, Synopsys is used in teaching and laboratories at over 600 universities.

FPGA implementation of the pixel purity index algorithm

Abstract: The Pixel Purity Index (PPI) is an algorithm employed in remote sensing for analyzing hyperspectral images. Particularly for low-resolution imagery, a single pixel usually covers several different materials, and its observed spectrum is (to a good approximation) a linear combination of a few pure spectral shapes. The PPI algorithm tries to identify these pure spectra by assigning a pixel purity index to each pixel in the image; the spectra for those pixels with a high index value are candidates for basis elements in the image decomposition. The PPI algorithm is extremely time consuming but is a good candidate for parallel hardware implementation due to its high volume of independent dot-product calculations. This article presents two parallel architectures we have developed and implemented on the Wildforce board. The first one is based on bit-serial arithmetic operators and the second deals with standard operators. Speed-up factors of up to 80 have been measured for these hand-coded architectures. In addition,the second version has been synthesized with the Streams-C compiler. The compiler translates a high level algorithm expressed in a parallel C extension into synthesizable VHDL. This comparison provides an interesting way of estimating the tradeoff between a traditional approach which tailors the design to get optimal performance and a fully automatic approach which aims to generate a correct design in minimal time.