Showing papers on "Wafer published in 1994"

Patterned susceptor to reduce electrostatic force in a CVD chamber

Abstract: A susceptor or other semiconductor wafer processing and/or transfer support platform includes a surface pattern having two or more regions of high and low elevation. The regions of high and low elevations can be rectangular/square dimpled patterns having tops coplanar with one another to support a semiconductor wafer for processing. The high and low regions can also be a wave form appearing to emanate from a point, where each of the wave crests form an imaginary plane on which a wafer to be processed can rest. The combination of high and low regions increases the average spacing between the wafer and the susceptor and reduces or eliminates the capacitive coupling (or sticking force) between processing hardware and a substrate (wafer) created by electrical fields during processing. The dimpled patterns are created by machining and can be created by using chemical and electrochemical etching of the wafer handling surfaces of processing hardware pieces.

High density plasma CVD and etching reactor

Abstract: The disclosure relates to an RF inductively coupled plasma reactor including a vacuum chamber (102) for processing a wafer (82), one or more gas sources (98, 100) for introducing into the chamber reactant gases, and an antenna (80) capable of radiating RF energy into the chamber to generate a plasma therein by inductive coupling, the antenna lying in a two-dimensionally curved surface. In another embodiment a plasma reactor includes apparatus for spaying a reactant gas at a supersonic velocity toward the portion of the chamber overlying the wafer. In a further embodiment a plasma reactor includes a planar spray showerhead for spraying a reactant gas into the portion of the chamber overlying the wafer with plural spray nozzle openings facing the wafer, and plural magnets in an interior portion of the planar spray nozzle between adjacent ones of the plural nozzle openings, the plural magnets being oriented so as to repel ions from the spray nozzle openings.

Two‐dimensional modeling of high plasma density inductively coupled sources for materials processing

Abstract: Inductively coupled plasma sources are being developed to address the need for high plasma density (1011–1012 cm−3), low pressure (a few to 10–20 mTorr) etching of semiconductor materials. One such device uses a flat spiral coil of rectangular cross section to generate radio‐frequency (rf) electric fields in a cylindrical plasma chamber, and capacitive rf biasing on the substrate to independently control ion energies incident on the wafer. To investigate these devices we have developed a two‐dimensional hybrid model consisting of electromagnetic, electron Monte Carlo, and hydrodynamic modules; and an off line plasma chemistry Monte Carlo simulation. The results from the model for plasma densities, plasma potentials, and ion fluxes for Ar, O2, Ar/CF4/O2 gas mixtures will be presented.

Gas-Source Molecular Beam Epitaxy of GaNxAs1-x Using a N Radical as the N Source

Abstract: We propose the application of GaNAs as a novel material fabricated on a Si wafer. It is a direct-transition type semiconductor, and can be lattice-matched to Si. Therefore, it is valid for use in the active region of light-emitting devices fabricated on Si. In this letter, GaNAs with a low N content is grown on a GaAs wafer to explore the gas-source molecular beam epitaxy under which a N radical is used as the N source. As a consequence, GaNAs with a N content up to 1.5% is grown, even though the conductance of the N-radical beam cell is fixed at a very low value. The bowing parameter of the bandgap is experimentally evaluated at 18 eV.

Very high‐efficiency semiconductor wafer‐bonded transparent‐substrate (AlxGa1−x)0.5In0.5P/GaP light‐emitting diodes

Abstract: Data are presented demonstrating the operation of transparent‐substrate (TS) (AlxGa1−x)0.5In0.5P/GaP light‐emitting diodes (LEDs) whose efficiency exceeds that afforded by all other current LED technologies in the green to red (560–630 nm) spectral regime. A maximum luminous efficiency of 41.5 lm/W (93.2 lm/A) is realized at λ∼604 nm (20 mA, direct current). The TS (AlxGa1−x)0.5In0.5P/GaP LEDs are fabricated by selectively removing the absorbing n‐type GaAs substrate of a p‐n (AlxGa1−x)0.5In0.5P double heterostructure LED and wafer bonding a ‘‘transparent’’ n‐GaP substrate in its place. The resulting TS (AlxGa1−x)0.5In0.5P/GaP LED lamps exhibit a twofold improvement in light output compared to absorbing‐substrate (AS) (AlxGa1−x)0.5In0.5P/GaAs lamps.

Epitaxial layer transfer by bond and etch back of porous Si

Abstract: We demonstrate a novel method for bond and etch back silicon on insulator in which an epitaxial Si layer over porous Si is transferred onto a dissimilar substrate by bonding and etch back of porous Si. The highest etching selectivity (100 000:1) between the porous Si and the epitaxial layer is achieved by the alkali free solution of HF, H2O2, and H2O which is essential for this single etch‐stop method to produce a submicron‐thick active layer with superior thickness uniformity (473±14 nm) across a 5 in. silicon‐on‐insulator wafer.

Supervisory run-to-run control of polysilicon gate etch using in situ ellipsometry

Abstract: Polysilicon gate etch is a critical manufacturing step in the manufacturing of MOS devices because it determines the tolerance limits on MOS circuit performance. The etch used in the current study suffers from machine aging, which causes processing results to drift with time. Performing the etch for the same time with fixed process setpoints (recipe) for all wafers would produce unsatisfactory results. Thus, an in situ ellipsometer was employed with a new run-to-run supervisory controller, termed predictor corrector control (PCC), to eliminate the impact of machine and process drift. A novel modeling technique was used to predict uniformity from the ellipsometry data collected at a single site on the wafer. Predictive models are employed by the PCC supervisory controller to generate optimal settings (recipe) for every wafer which will achieve a target mean etch rate, while maintaining a spatially uniform etch. A 200 wafer experiment was conducted to demonstrate the benefits of process control. Implementation of PCC resulted in a 36% decrease in standard deviation from target for the mean etch rate. In addition, the data indicates that controlling etch rate may improve the control and uniformity of the line width change. >

Three dimensional processor using transferred thin film circuits

Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.

Wafer polishing method and apparatus

Abstract: A wafer polishing apparatus includes a wafer polishing assembly having a plurality of wafer carriers for substantially simultaneously polishing a plurality of wafers against a rotating polishing surface. A plurality of wafers to be polished are substantially simultaneously loaded into the plurality of wafer carriers by wafer holding apparatus of an index table. Similarly, a plurality of wafer carriers are substantially simultaneously unloaded into wafer holding apparatus of the index table. The wafer carriers are individually computer controlled for exact polishing and different polishing requirements can be met at the same time by different wafer carriers.

Tribology Analysis of Chemical‐Mechanical Polishing

Abstract: To better understand the variation of material removal rate on a wafer during chemical-mechanical polishing (CMP), knowledge of the stress distribution on the wafer surface is required. The difference in wafer-surface stress distributions could be considerable depending on whether or not the wafer hydroplanes during polishing. This study analyzes the fluid film between the wafer and pad and demonstrates that hydroplaning is possible for standard CMP processes. The importance of wafer curvature, slurry viscosity, and rotation speed on the thickness of the fluid film is also demonstrated.

Vacuum processing apparatus

Abstract: A vacuum processing apparatus includes: a processing chamber for performing a film formation process to a semiconductor wafer in a vacuum; a mounting member provided in the processing chamber and having a mounting surface for mounting a target object; an electrostatic chuck, provided to the mounting surface of the mounting member, for chucking the semiconductor wafer; a heating mechanism for heating the semiconductor wafer; and a processing gas supply mechanism for supplying a processing gas for performing the film formation process to the semiconductor wafer into the processing chamber. The mounting member has a base, a first insulating layer formed on the surface of the base, and a second insulating layer formed on the first insulating layer, and has a conductive layer between the first insulating layer and the second insulating layer on the mounting surface side of the mounting member to obtain the above electrostatic chuck constituted by the first insulating layer, the second insulating layer, and the conductive layer, and the heating mechanism has a heating member provided between the first insulating layer and the second insulating layer on the lower surface side of the mounting member.

Micromachined silicon electrostatic chuck

Abstract: An electrostatic chuck is faced with a patterned silicon plate 11, createdy micromachining a silicon wafer, which is attached to a metallic base plate 13. Direct electrical contact between the chuck face 15 (patterned silicon plate's surface) and the silicon wafer 17 it is intended to hold is prevented by a pattern of flat-topped silicon dioxide islands 19 that protrude less than 5 micrometers from the otherwise flat surface of the chuck face 15. The islands 19 may be formed in any shape. Islands may be about 10 micrometers in diameter or width and spaced about 100 micrometers apart. One or more concentric rings formed around the periphery of the area between the chuck face 15 and wafer 17 contain a low-pressure helium thermal-contact gas used to assist heat removal during plasma etching of a silicon wafer held by the chuck. The islands 19 are tall enough and close enough together to prevent silicon-to-silicon electrical contact in the space between the islands, and the islands occupy only a small fraction of the total area of the chuck face 15, typically 0.5 to 5 percent. The pattern of the islands 19, together with at least one hole 12 bored through the silicon veneer into the base plate, will provide sufficient gas-flow space to allow the distribution of the helium thermal-contact gas.

Fundamentals of Semiconductor Processing Technology

Abstract: 1: Semiconductor Crystals. 1.1. Crystals and Crystallographic Orientations. 1.2. The Silicon Crystal. 1.3. Wafer Preparation. 1.4. Compound Semiconductors. 2: Thermal Oxidation and Nitridation. 2.1. SiO2 and SiO2-Si Interface. 2.2. Thermal Oxidation. 3: Thin Film Deposition. 3.1. Chemical Vapor Deposition. 3.2. Chemical-Physical Deposition Processes. 3.3. Physical-Vapor Deposition. 4: Lithography. 4.1. Optical Lithography. 4.2. Resolution Enhancement Techniques. 4.3. Electron-Beam Lithography. 4.4. X-Ray Lithography. 4.5. Ion-Beam Lithography. 5: Contamination Control and Etch. 5.1. Clean Processes. 5.2. Etching. 6: Ion Implantation. 6.1. Principle of Operation. 6.2. Energy Loss and Range Distribution. 6.3. Crystal Damage and Dopant Activity. 7: Diffusion. 7.1. Point Defects. 7.2. Fick's Laws. 7.3. Non-Constant Diffusivity. 7.4. Diffusion in Polysilicon. 7.5. Diffusion in Insulators. 7.6. Diffusion Sources. 7.7. Gettering in Silicon. 8: Contact and Interconnect Technology. 8.1. Contact Metallurgy. 8.2. Poly-Metal Dielectrics. 8.3. Metal Interconnects. 8.4. Inter-Level Dielectrics. 8.5. Multi-Level Metals. 8.6. Reliability Considerations. Subject Index.

Charge Damage Caused by Electron Shading Effect

Abstract: An antenna covered with photoresist patterns having high-aspect-ratio openings caused charge damage to the gate oxide in various processing plasmas. This damage increased with the pattern's aspect ratio, and occurred even when the test wafer was cut into chips about 5 mm square and mounted on a wafer with insulation. These results prove the electron shading model: the photoresist patterns shade the antenna from electrons of oblique incidence, resulting in local charging occurring without a wafer-scale voltage difference, which is essential for conventional charging. The damaging current from this mechanism increased by a factor of more than ten with a decrease in the gate oxide thickness only from 8 nm to 6 nm, implying that the degree of shading depends on the gate charging voltage. An improved model is proposed to accommodate this strong dependence.

Silicon wafers containing conductive feedthroughs

Abstract: Silicon wafers containing conductive feedthroughs of an hourglass shape located around their peripheries that can be incorporated into multichip modules that includes silicon wafer spacers having radial grooves for receiving cooling fluid.

Method and apparatus for cooling semiconductor wafers.

Abstract: A semiconductor wafer cooling pedestal has a wafer cooling surface which includes both an electrostatic chuck portion to hold the wafer securely to the pedestal during wafer cooling and a thermal transfer portion to cool the wafer. The entire wafer cooling surface of the pedestal is mirror finished to provide intimate contact between the pedestal cooling surface and the wafer, thereby providing efficient thermal transfer from the wafer to the pedestal without the need for placing a thermal transfer medium, such as Argon or other inert gas, between the wafer and the pedestal.

Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature

Abstract: Micromechanical smart sensor and actuator systems of high complexity become commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated to contain the readout circuits The individually-processed wafers can be assembled using wafer-to-wafer bonding and can be combined to one single functional electro-mechanical unit using through-wafer interconnect, provided that the processes involved comply with the constraints imposed by the proper operation of the active electrical and micromechanical subsystems This implies low-temperature wafer-to-wafer bonding and through-wafer interconnect Au/Si eutectic bonding has been investigated as it can conveniently be combined with bulk-micromachined through-wafer interconnect The temperature control in eutectic bonding has been shown to be critical

Process for producing surface micromechanical structures

Abstract: A method for fabricating surface-micromechanical structures wherein a sacrificial layer, in particular of silicon oxide, is deposited on a silicon substrate represented by a silicon wafer, the sacrificial layer being patterned. Onto the sacrificial layer, a second layer, in particular of polysilicon, is deposited and is likewise patterned. The sacrificial layer is removed in an etching operation by means of an etching medium which attacks the sacrificial layer but not the second layer, structures being formed as a result of which are free-standing above the silicon substrate at a distance equal to the thickness of the removed sacrificial layer and are anchored at certain sites on the silicon substrate. According to the invention, for the purpose of etching and exposing, the micromechanical structures are exposed to the vapor phase of a mixture of anhydrous hydrofluoric acid and water in a vapor-phase etching process. This makes it possible to dispense with laborious rinsing operations and sublimation operations.

Optimization of dry etching through the control of helium backside pressure

Abstract: In a dry non-isotropic etching process, backside cooling by helium controls the rate and uniformity of etching in a thermal silicon layer, the taper of profiles etched into silicon dioxide layers, and the dimension and uniformity of etched structures in a polycide or polysilicon layer, on the surface of a silicon wafer. Helium pressures from greater than 2 torr to more than 10 torr are satisfactorily utilized to produce these effects.

Wafer-handling apparatus having a resilient membrane which holds wafer when a vacuum is applied

Abstract: An apparatus for acquiring, holding, and releasing a wafer includes a soft resilient membrane that covers a horizontal backing plate. The lower face of the backing plate includes a number of recessed areas to which a vacuum can selectively be applied. To acquire a wafer, the wafer is elevated carefully until the upper side of the wafer contacts the lower side of the membrane. Next, a vacuum is applied to the recessed areas which sucks the resilient membrane into the recessed areas so that each recessed area becomes a suction cup that draws the wafer against the membrane. When the vacuum is replaced by ambient pressure, the resiliency of the membrane restores it to its original taut condition thereby releasing the wafer. The same apparatus can be used for uniformly polishing the lower face of the wafer by applying a pressurized fluid to the recessed areas during polishing, which causes the membrane to exert a uniform downward pressure on the wafer.

Shallow trench isolation process for high aspect ratio trenches

Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.

Wafer support fixtures for rapid thermal processing

Abstract: A fixture for supporting a semiconductor wafer during rapid thermal processing, comprising a two-piece assembly of parts, one of which is a silicon carbide wafer support section having a wafer contact face shaped by direct contact with a mold, during its formation by chemical vapor deposition. The other piece is a holding section shaped to keep the wafer support section in place within the reactor. The two-piece assembly improves thermal performance, compared with a one-piece fixture, because the rate of heat conduction across the gap between parts is always less than the rate of heat conduction through a one-piece fixture having the same dimensions.

Method of micro-machining an integrated sensor on the surface of a silicon wafer

Abstract: A method for micromachining the surface of a silicon substrate which encompasses a minimal number of processing steps. The method involves a preferential etching process in which a chlorine plasma etch is capable of laterally etching an N+ buried layer beneath the surface of the bulk substrate. Such a method is particularly suitable for forming sensing devices which include a small micromachined element, such as a bridge, cantilevered beam, membrane, suspended mass or capacitive element, which is supported over a cavity formed in a bulk silicon substrate. The method also permits the formation of such sensing devices on the same substrate as their controlling integrated circuits. This invention also provides novel methods by which such structures can be improved, such as through optimizing the dimensional characteristics of the micromachined element or by encapsulating the micromachined element.

Backside contact of sensor microstructures

Abstract: A sensor microstructure contact scheme is provided for making backside electrical, mechanical, fluidic, or other contact to mechanical microstructures. The contact scheme is applicable to pressure sensors, shear stress sensors, flow rate sensors, temperature sensors, resonant microactuators, and other microsensors and microactuators. The contact scheme provides a microelectromechanical sensor body and support structure for backside contact of the sensor body, and features a support wafer substrate having one or more through-wafer vias each with a lateral span on the dimension of microns and a span that is more narrow at the wafer front surface than at the wafer back surface. An insulating film covers a portion of the support wafer substrate and sidewalls of the vias--with the lateral via span at the front surface being open. The front surface of the support wafer substrate is bonded to the front surface of a sensor body wafer substrate, such that contact of the front surface of the sensor body wafer substrate may be made through the support wafer substrate vias from the back surface of the support wafer substrate. The sensor body wafer substrate is adapted to define a mechanical sensor microstructure, and comprises a plurality of isolated substrate regions, each region corresponding to one of the support wafer substrate through-wafer vias. Each such region is circumscribed by an edge of the mechanical sensor microstructure and an isolating border region. Contact made through one of the support wafer substrate through-wafer vias to the corresponding one of the sensor body substrate regions is isolated and thereby prevented from making contact to any other sensor body substrate region.

Electrodeposition apparatus with virtual anode

Abstract: An electrochemical etching step in a semiconductor device fabrication process increases the radius of curvature of edges of metal lines deposited on the semiconductor device. The metal lines are fabricated by forming a mask, electrodepositing the metal, and removing the mask, and the electrochemical etching step in performed subsequently. The increased radius of curvature of the metal lines simplifies subsequent planarization and decreases line-to-line capacitance, thereby enhancing device performance. In an apparatus for performing the fabrication process, wires sown into a gasket which secures the semiconductor wafer and prevents electrolyte leakage, allows the gasket to function also as a component of the cathode. A more uniform metal deposition is created by a virtual anode, i.e., a metal plate having an aperture and being located between the anode and the cathode.

Test analysis apparatus and analysis method for semiconductor wafer using OBIC analysis

Abstract: A test analysis apparatus for OBIC analysis and luminous analysis from a rear surface of a semiconductor wafer. According to the present invention, a semiconductor wafer is mounted on a wafer chuck and a probe card which has metallic needles and which is movable along the X, Y, and Z axes supplies a test pulse signal to respective electrode pads on the front surface of the semiconductor wafer. Then, current generated in the semiconductor wafer is detected at the electrode pads. Optical analysis, such as irradiation with a light beam, detection of reflected light, detection of light generated in the semiconductor wafer and the like, is performed from the rear side of the semiconductor wafer, thereby enabling analysis of a failure or a defect of a defective portion while the semiconductor wafer is in actual operating conditions.

Focus ring for semiconductor wafer processing in a plasma reactor

Abstract: In one aspect, the invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a pedestal focus ring surrounding the periphery of the wafer for reducing the process etch rate near the wafer periphery, and plural openings through the pedestal focus ring which permit passage therethrough of particulate contamination, thereby reducing accumulation of particulate contamination near the wafer periphery. In another aspect, in order to reduce corrosive wear of the chamber walls, a removable gas distribution focus ring shields the side walls of the plasma reactor from reactive gases associated with processing of the semiconductor wafer.

Wafer tray and ceramic blade for semiconductor processing apparatus

Abstract: A semiconductor wafer processing system for processing wafers from a wafer storage cassette includes a wafer transfer chamber; a wafer storage elevator within the transfer chamber; one or more wafer processing chambers; and a wafer transfer apparatus for transferring a wafer between a standard storage cassette adjacent and outside the transfer chamber and the elevator, and between the elevator and the processing chamber. The storage chamber pressure varies between atmospheric when accepting wafers from outside, and a subatmospheric pressure when transferring wafers to or from a processing chamber. The transfer apparatus includes a robot arm; a thin flat wafer carrying blade at the leading end of the robot arm configured for engaging a wafer from the storage cassette or the elevator; and a wafer support tray configured for removable engagement with the blade and for engaging and positively positioning a wafer from the elevator, or a support pedestal within a processing chamber. When the transfer apparatus moves a wafer between the elevator and a processing chamber in an evacuated environment, the tray is engaged with the blade and helps retain the wafer during transit. When wafers are transferred between the cassette and the elevator at atmospheric pressure the tray is disengaged from the blade and placed in a rest position on the elevator, and the wafer transfer is performed by means of the blade alone with a vacuum pick integral to the blade. The blade includes upper and lower halves together defining vacuum channels and capacitive position sensors.

Bonded wafer processing with metal silicidation

Abstract: Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon-nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers.