Showing papers by "Adrian Powell published in 2008"

Recent progress in SiC DMOSFETs and JBS diodes at Cree

Abstract: This paper discusses the recent progress in large area silicon carbide (SiC) DMOSFETs and junction barrier Schottky (JBS) diodes 12 kV and 10 kV SiC DMOSFETs have been produced with die areas greater than 064 cm2 SiC JBS diode dies also rated at 12 kV and 10 kV have been produced with die areas exceeding 15 cm2 These results demonstrate that SiC power devices provide a significant leap forward in performance for industrial electronics applications At 12 kV, SiC DMOSFETs offer a reduction of power loss of greater than 50 % with dies less than half the size when compared to silicon (Si) IGBTs The SiC JBS diodes offer significant reductions in reverse recovery losses At 10 kV, there are no Si devices that can compete with SiC on a single device basis Data on 12 kV and 10 kV devices are presented along with future trends

Performance and Stability of Large-Area 4H-SiC 10-kV Junction Barrier Schottky Rectifiers

Abstract: The forward and reverse bias dc characteristics, the long-term stability under forward and reverse bias, and the reverse recovery performance of 4H-SiC junction barrier Schottky (JBS) diodes that are capable of blocking in excess of 10 kV with forward conduction of up to 10 A at a forward voltage of less than 3.5 V (at 25degC) are described. The diodes show a positive temperature coefficient of resistance and a stable Schottky barrier height of up to 200degC. The diodes show stable operation under continuous forward current injection at 20 A/cm2 and under continuous reverse bias of 8 kV at 125degC. When switched from a 10-A forward current to a blocking voltage of 3 kV at a current rate-of-fall of 30 A/mus, the reverse recovery time and the reverse recovery charge are nearly constant at 300 ns and 425 nC, respectively, over the entire temperature range of 25degC-175degC.

100 mm 4HN-SiC Wafers with Zero Micropipe Density

Abstract: Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.

Development of Large Area (up to 1.5 cm2) 4H-SiC 10 kV Junction Barrier Schottky Rectifiers

Abstract: DC characteristics and reverse recovery performance of 4H-SiC Junction Barrier Schottky (JBS) diodes capable of blocking in excess of 10 kV with forward conduction of 20 A at a forward voltage of less than 4 V are described. Performance comparisons are made to a similarly rated 10 kV 4H-SiC PiN diode. The JBS diodes show a significant improvement in reverse recovery stored charge as compared to PiN diodes, showing half of the stored charge at 25°C and a quarter of the stored charge at 125°C when switched to 3 kV blocking. These large area JBS diodes were also employed to demonstrate the tremendous advances that have recently been made in 4H-SiC substrate quality.

State of the Art 10 kV NMOS Transistors

Abstract: Rapidly improving 4 H-SiC material quality and a maturing MOS process/design have enabled the development of the largest 10 kV MOSFET to date and the first 10 kV n-IGBT capable of flowing 10 A and 4 A, respectively, with very low on- resistances. With 20 V on the gate, both devices have aVp~ 5V with a positive temperature coefficient for on-resistance that facilitates their use in a parallel configuration. Each device has its own advantages. The conductivity modulated n-IGBT offers higher current density operation (up to 100 A/cm ) while the majority carrier MOSFET offers extremely fast 5 kV switching with only 140 nsec of turn-off time and a manageable 160 W/cm of dissipated power at 20 kHz. These exciting results indicate that the 10 kV SiC NMOS switches may potentially revolutionize emerging high voltage, high frequency power electronics.

Critical Technical Issues in High Voltage SiC Power Devices

Abstract: In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.

SiC Epitaxial Growth on Multiple 100-mm Wafers and its Application to Power-Switching Devices

Abstract: The development of SiC bulk and epitaxial materials is reviewed with an emphasis on epitaxial growth using high-throughput, multi-wafer, vapor phase epitaxial (VPE) warm-wall planetary reactors. It will be shown how the recent emergence of low-cost high-quality 100-mm diameter epitaxial SiC wafers is enabling the economical production of advanced wide-bandgap Power–Switching devices.

Low bottom face dislocation bulk growth sic wafer

Abstract: PROBLEM TO BE SOLVED: To provide, in a seed sublimation system, a manufacturing method of a high quality silicon carbide bulk single crystal of a low bottom face defect level. SOLUTION: This high quality SiC wafer having a bottom face dislocation density of less than 500 cm -2 on a wafer and at least 1 square inch continuous surface region is obtained by forming a SiC boule having a diameter of a little larger than 3 inches by a seed sublimation growth method, then slicing the boule at an angle between about 2° and 12° to 0001 plane, and further polishing it. COPYRIGHT: (C)2009,JPO&INPIT

3 inch silicon carbide wafer having low 1c screw dislocation

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carbide bulk single crystal wherein the crystal formed by a sublimation system using a seed crystal in order to reduce the total number of defects in the manufactured crystal has a low 1c screw dislocation level, a larger size and a high quality. SOLUTION: The high quality SiC single crystal wafer is a polytype selected from the group consisting of 3C, 4H, 6H, 2H and 15R polytypes and has a diameter of at least 76.2 mm (about 3 in.) and a 1c screw dislocation density of less than about 2,000 cm -2 . COPYRIGHT: (C)2009,JPO&INPIT