Showing papers by "Anabela Veloso published in 2006"

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

Abstract: A complete determination of the effective work functions (WF) of NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si on HfSiON and on SiO/sub 2/ is presented. Conditions for formation of fully silicided (FUSI) gates for NiSi/sub 2/, NiSi, Ni/sub 3/Si/sub 2/, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si crystalline phases were identified. A double thickness series (HfSiON/SiO/sub 2/) was used to extract WF on HfSiON accounting for charge effects. A strong effect on WF of Ni content is observed for HfSiON, with higher WF for the Ni-rich silicides suggesting unpinning of the Fermi level. A mild dependence is observed for SiO/sub 2/. While all Ni-rich silicides have adequate WF for pMOS applications, Ni/sub 2/Si is most attractive due to its low formation temperature, lower volume expansion and ease of integration. Similar threshold voltages (-0.3 V) were obtained on Ni/sub 2/Si and Ni/sub 31/Si/sub 12/ FUSI HfSiON pMOSFETS.

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS: $\hbox{Ni}_{2}\hbox{Si}$ , and $\hbox{Ni}_{31}\hbox{Si}_{12}$ ) on HfSiON

Abstract: The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni31Si12 FUSI gates on p-channel MOS (PMOS) with good Vt control to short gate lengths (LG=50 nm, linear Vt of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni2Si or Ni31 Si12 on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni2Si or Ni31Si12 FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% Ion improvement at Ioff=100 nA/mum) was obtained for Ni 31Si12 compared to Ni2Si FUSI gates, as well as a Vt reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS

Linewidth effect and phase control in Ni fully silicided gates

Abstract: The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni2Si, and Ni31 Si12. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and Vt control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni2Si processes with excessive thermal budgets, resulting in significant Vt shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth Vt rolloff characteristics was demonstrated for NiSi, Ni2Si, and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni2Si are less than or equal to 25 degC, whereas a single-phase Ni31Si12 is obtained over an ~200degC temperature range

Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

Abstract: This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-VT applications) have been achieved (17ps at VDD=1.1V and 20pA/?m Ioff), meeting the ITRS 45nm node requirement for low power CMOS.

Method for gate electrode height control

Abstract: One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate. The method further comprises applying an additional layer of oxide on top of the sacrificial layer. The method further comprises covering with a material the semiconductor substrate provided with the at least one gate electrode having the sacrificial cap layer with the additional oxide layer on top. The method further comprises performing a CMP planarization step. The method further comprises removing at least the material and the additional layer of oxide until on top of each of the at least one gate electrode the sacrificial cap layer is exposed. The method further comprises removing the sacrificial cap layer from each of the at least one gate electrode, yielding each of the at least one gate electrode still having the given height.

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

Abstract: This work presents the first comprehensive evaluation of the manufacturability and reliability of dual WF phase controlled Ni-FUSI/HfSiON CMOS (NMOS: NiSi; PMOS: Ni2Si and Ni31 Si12 evaluated) for the 45 nm node. RTP1 and poly/spacer height were identified as the most critical process control parameters in our flow. We demonstrate that a novel sacrificial SiGe cap addition to the flow (improved poly-Si/spacer height control) opens the RTP1 process window from ~5degC to ~20degC for gate lengths down to 45nm, making scalable dual WF CMOS Ni-FUSI manufacturable. We demonstrate Vt control with sigma~19mV (including wafer to wafer variation, N=1000, 45 nm devices) for NMOS (NiSi), and sigma~21mV for PMOS. TDDB and NBTI reliability evaluation of NiSi and, for the first time, of Ni2Si and Ni31Si12 was done. ~1V or larger operating voltages (Vop) were extrapolated for a 10 years lifetime. Using a higher back-end thermal budget showed no reliability degradation

Low Power CMOS Featuring Dual Work Function FUSI on HfSiON and 17ps Inverter Delay

Abstract: We report record unloaded ring oscillator delay (17ps at VDD = 1.1V and 20pA/mum Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report presented in A. Lauwers et al. (2005). First, we have improved the (unstrained) devices Idsat to be 560/245muA/mum for nMOS/pMOS at an Ioff = 20pA/mum and VDD=1.1V. Second, we demonstrate that the use of metal gates enables a reduction of the junction anneal temperature, yielding an Lgmin reduction of 7nm/14nm for nMOS/pMOS over our poly-Si/SiON reference. We also report for the first time that metal gate on HfSiON devices can outperform optimized conventional poly-Si/SiON devices by up to 25% in unloaded ring oscillator speed. Finally, our study shows that there is no intrinsic difference between Ni-FUSI compared to inserted metal gates (TiN, TaN)

A Novel CMP-Less Integration Scheme For Dual Work Function Ni-FUSI CMOS

Abstract: The authors demonstrate a novel CMP-less FUSI integration scheme which uses a spin-on sacrificial material for planarization showing 45nm gate length Ni-rich FUSI pMOS and NiSi FUSI nMOS transistors on HfSiON. This new scheme does not require CMP but remains compatible with phase-controlled dual-WF CMOS with independent silicidation of the S/D and the gate. This approach uses very selective dry etch processes that result in uniform poly-Si height, widening the RTP process window of NiSi FUSI from 5degC (Kittl et al., 2005) for the CMP approach to 15degC, without additional process complexity. Furthermore it is less disruptive compared to the standard CMP approach making it more compatible with stressed liners