Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

Deposits of clastic carbonate-dominated (calciclastic) sedimentary slope systems in the rock record have been identified mostly as linearly-consistent carbonate apron deposits, even though most ancient clastic carbonate slope deposits fit the submarine fan systems better. Calciclastic submarine fans are consequently rarely described and are poorly understood. Subsequently, very little is known especially in mud-dominated calciclastic submarine fan systems. Presented in this study are a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) that reveals a >250 m thick calciturbidite complex deposited in a calciclastic submarine fan setting. Seven facies are recognised from core and thin section characterisation and are grouped into three carbonate turbidite sequences. They include: 1) Calciturbidites, comprising mostly of highto low-density, wavy-laminated bioclast-rich facies; 2) low-density densite mudstones which are characterised by planar laminated and unlaminated muddominated facies; and 3) Calcidebrites which are muddy or hyper-concentrated debrisflow deposits occurring as poorly-sorted, chaotic, mud-supported floatstones. These

Phd by thesis

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

A strain sensor has been fabricated from a polymer nanocomposite with multiwalled carbon nanotube (MWNT) fillers. The piezoresistivity
of this nanocomposite strain sensor has been investigated based on an improved three-dimensional (3D) statistical resistor network
model incorporating the tunneling effect between the neighboring carbon nanotubes (CNTs), and a fiber reorientation model. The
numerical results agree very well with the experimental measurements. As compared with traditional strain gauges, much higher sensitivity
can be obtained in the nanocomposite sensors when the volume fraction of CNT is close to the percolation threshold. For a small
CNT volume fraction, weak nonlinear piezoresistivity is observed both experimentally and from numerical simulation. The tunneling
effect is considered to be the principal mechanism of the sensor under small strains.

Tunneling effect in a polymer/carbon nanotube nanocompositestrain sensor

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

The heat-removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters ≤200 μm. An experimental investigation with uniform and double-side heat flux at Reynolds numbers ≤1,000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. The following structures were tested: parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 μm and fluid structure heights of 100–200 μm. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin in-line structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks having a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from >200 W/cm2 at 1 cm2 and >50 μm interconnect pitch to <100 W/cm2 at 4 cm2. From experimental data, friction factor and Nusselt number correlations were derived for pin fin in-line and staggered structures.

Interlayer cooling potential in vertically integrated packages

The heat removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters les 200 mum. An experimental investigation with uniform and double-side heat flux at Reynolds numbers les 1000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. Parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mum and fluid structure heights of 100 to 200 mum were tested. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin inline structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks with a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from >200 W/cm2 at 1 cm2 and >50 mum interconnect pitch to <100 W/cm2 at 4 cm2.

Forced convective interlayer cooling in vertically integrated packages

3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so- called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high- performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBESreg) is a typical example for the need of such mixed approaches.

Through silicon via technology — processes and reliability for wafer-level 3D system integration

The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed layer nature on filling ratio and void formation will be discussed with respect to via diameter and via depth. Based on the spherolyte Cu200 the electrolyte for the copper electrochemical deposition was modified for good filling behavior. Thermomechanical modeling and simulation was performed for reliability assessment.

High aspect ratio TSV copper filling with different seed layers

This paper investigates the thermo-mechanical reliability of inter-chip-vias (ICV) for 3D chip stacking after processing and under external thermal loads relevant for the envisaged field of application (mobile, automotive) by Finite Element simulation. First the materials are characterised by nano-indentation to determine elasto-plastic data. Finite Element simulations are used to reproduce these data and to extract local material properties like E-modulus and yield stress. Accumulated plastic strain is used as failure indicator under periodic thermal loading of an ICV. Geometrical, material and process-related parameters are varied to obtain first design guidelines for this new technology. The locations of stress and strain accumulation are given.

Bernhard Wunderle

Papers

Interlayer cooling potential in vertically integrated packages

Forced convective interlayer cooling in vertically integrated packages

Through silicon via technology — processes and reliability for wafer-level 3D system integration

High aspect ratio TSV copper filling with different seed layers

Thermo-Mechanical Reliability of 3D-integrated Microstructures in Stacked Silicon