Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.

Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation

The ever-increasing demands of digital computing and wireless communication have been driving the semiconductor technology to change with each passing day. Modern electronic systems integrate more complex components and devices, which results in a very complex electromagnetic (EM) field environment. EM compatibility has become one of the major issues in ICs redesign, mainly due to the lack of efficient and accurate simulation tools and expertise on noise reduction and immunity improvement. This paper reviews the state of the arts of IC, electronic package, and printed circuit board simulation and modeling technologies. It summarizes the modeling technologies for both available structures [multilayered power-ground planes and macromodeling of interconnect (INC)] and novel structures (nano-INCs and 3-D ICs based on through-silicon via technology). It also illustrates the trends of simulation and modeling technologies in EM compatibility, signal integrity, and power integrity.

Progress Review of Electromagnetic Compatibility Analysis Technologies for Packages, Printed Circuit Boards, and Novel Interconnects

The via-plate capacitance for a via transition to a multilayer printed circuit board is evaluated analytically in terms of higher order parallel-plate modes. The Green's function in a bounded coaxial cavity for a concentric magnetic ring current is first derived by introducing reflection coefficients for cylindrical waves at the inner and outer cavity walls. These walls can be perfect electric conductor (PEC)/perfect magnetic conductor(PMC) or a nonreflective perfectly matched layer. By further assuming a magnetic frill current on the via-hole in the metal plate, an analytical formula is derived for the via barrel-plate capacitance by summing the higher order modes in the bounded coaxial cavity. The convergence of the formula with the number of modes, as well as with the radius of the outer PEC/PMC wall is discussed. The analytical formula is validated by both quasi-static numerical methods and measurements. Furthermore, the formula allows the investigation of the frequency dependence of the via-plate capacitance, which is not possible with quasi-static methods.

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Analytical Evaluation of Via-Plate Capacitance for Multilayer Printed Circuit Boards and Packages

An irregular plate pair with multiple vias is analyzed by the segmentation method that divides the plate pair into a plate domain and via domains. In the via domains, all the parallel-plate modes are considered, while in the plate domain, only the propagating modes are included to account for the coupling among vias and the reflection from plate edges. Boundary conditions at both vias and plate edges are enforced and all parasitic components of via circuit are expressed analytically in terms of parallel-plate modes. The work presented in this paper indicates that a previous physics-based via circuit model from intuition is a low-frequency approximation. Analytical and numerical simulations, as well as measurements, have been used to validate the intrinsic via circuit model.

An Intrinsic Circuit Model for Multiple Vias in an Irregular Plate Pair Through Rigorous Electromagnetic Analysis

In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structure's impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it Full-wave methods are often employed to study the power integrity problem While full-wave methods can be accurate, they are time and memory consuming The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived This allows both frequency and transient responses to be done with SPICE simulation

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An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

Differential and common-mode transfer impedances are proposed herein to analyze noise coupled to (from) the dc power-bus from (to) via transitions in differential signals. Expressions for the two transfer impedances in terms of conventional single-ended transfer impedances are derived and verified through measurements, full-wave finite-difference time-domain (FDTD) simulations and an analytical cavity model. Some properties of the differential and common-mode transfer impedances are investigated to facilitate engineering design. The impact of signal current imbalances on power-bus noise and the benefit of differential signals as compared to single-ended signals are quantified.

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Coupling between differential signals and the dc power-bus in multilayer PCBs

This paper describes the evaluation of the susceptibility of a cavity with an aperture using the finite-difference time-domain (FDTD) method and experimentally. To reduce the computing time, the FDTD method is used for the radiation from the cavity and the susceptibility is obtained by using the reciprocity theorem. The cavity used here is modeled after a full-tower desktop enclosure with a 3.5-in bay. The susceptibility characteristics are evaluated by measuring outputs of a monopole antenna and transmission lines installed in the cavity. The susceptibility characteristics, using a three-dimensional (3-D) map, are studied from the computed and the measured results by applying slowly rotating electromagnetic fields to the cavity on a turntable. Measured and modeled results are in good agreement, indicating the merits of the proposed approach for susceptibility/immunity evaluation. Moreover, some discussions are made to check the susceptibility mechanism.

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Susceptibility characterization of a cavity with an aperture by using slowly rotating EM fields: FDTD analysis and measurements

In a high-speed connector system, coupling to an adjacent cable-connector system is not uncommon. It is essential to understand and quantify this coupling path in order to mitigate the coupling. Though simulation based methods are widely used, such an approach is generally very time consuming and computationally resource hungry. A measurement based method for quantifying the EMI coupling path between a highspeed connector and an adjacent connector on the same board is presented. This is based on measured S-parameters for the mode conversion representing the coupling from the differential mode in one connector to the antenna mode current on the other connector-cable system. The method is validated on two test structures comparing estimated and measured radiated field emissions.

A Method to Quantify the Coupling between DVI and HDMI Connectors

Electromagnetic interference (EMI) is correlated with mode conversion, from differential-mode signals to common-mode currents and further to antenna-mode currents on the outside of cables or enclosures. This paper presents methods to quantify the mode conversion caused by discontinuities in the digital visual interface (DVI) signal link. These discontinuities are mostly present in the DVI connector, the DVI cable, and the connector–cable interface. A systematic approach was developed in this study to isolate and identify the different coupling paths in a high-speed interface (in this case, DVI is shown) and also to identify which discontinuity is most critical to mitigate EMI. The method developed in this study can be used for any high-speed interface in modern communication systems.

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Chen Wang

Papers

An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

Coupling between differential signals and the dc power-bus in multilayer PCBs

Susceptibility characterization of a cavity with an aperture by using slowly rotating EM fields: FDTD analysis and measurements

A Method to Quantify the Coupling between DVI and HDMI Connectors

EMI Analysis of DVI Link Connectors