다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

About the Author.Foreword.Preface.Glossary.1. Introduction.2. Video Formats and Quality.3. Video Coding Concepts.4. The MPEG-4 and H.264 Standards.5. MPEG-4 Visual.6. H.264/MPEG-4 Part 10.7. Design and Performance.8. Applications and Directions.Bibliography.Index.

H.264 and MPEG-4 Video Compression: Video Coding for Next-generation Multimedia

We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.

https://www.pagiamtzis.com/pubs/pagiamtzis-jssc2006.pdf

Content-addressable memory (CAM) circuits and architectures: a tutorial and survey

Advances in wireless communication technologies, such as wearable and implantable biosensors, along with recent developments in the embedded computing area are enabling the design, development, and implementation of body area networks. This class of networks is paving the way for the deployment of innovative healthcare monitoring applications. In the past few years, much of the research in the area of body area networks has focused on issues related to wireless sensor designs, sensor miniaturization, low-power sensor circuitry, signal processing, and communications protocols. In this paper, we present an overview of body area networks, and a discussion of BAN communications types and their related issues. We provide a detailed investigation of sensor devices, physical layer, data link layer, and radio technology aspects of BAN research. We also present a taxonomy of BAN projects that have been introduced/proposed to date. Finally, we highlight some of the design challenges and open issues that still need to be addressed to make BANs truly ubiquitous for a wide range of applications.

Body Area Networks: A Survey

In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-/spl mu/m single-poly and six-metal CMOS process with a core area of 1.76/spl times/1.76 mm/sup 2/, including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s.

/pdf/a-1-gs-s-fft-ifft-processor-for-uwb-applications-3dn8752s6c.pdf

A 1-GS/s FFT/IFFT processor for UWB applications

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.

/pdf/an-all-digital-phase-locked-loop-for-high-speed-clock-1tt9sx85a2.pdf

An all-digital phase-locked loop for high-speed clock generation

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum2 , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements

/pdf/design-of-an-fft-ifft-processor-for-mimo-ofdm-systems-1tjm3xe2ij.pdf

Design of an FFT/IFFT Processor for MIMO OFDM Systems

The explosive demand in wireless-capable devices, especially with the proliferation of multiple standards, indicates a great opportunity for adoption of wireless technology at a mass-market level. The communication devices of both today and the future will have not only to allow for a variety of applications, supporting the transfer of characters, audio, graphics, and video data, but they will also have to maintain connection with many other devices rather than with a single base station, in a variety of environments. Moreover, to provide various services from different wireless communication standards with higher capacities and higher data-rates, fully integrated and multifunctional wireless devices will be required. Multifunctional circuits and systems can be made profitable by a large scale of integration, elimination of external components, reduction of silicon area, and extensive reuse of resources. Integration of (Bi)CMOS transceiver RF front-end and analog baseband circuits with computing CMOS circuits on the same silicon chip further reduces costs of multifunctional mobile devices. However, as batteries continue to determine the lifetime and size of mobile equipment, further extension of capabilities of wearable and wireless devices will depend critically on the integrated circuits and systems solutions. The demand for multifunctional and multi-mode wireless-capable devices is accompanied by many significant challenges at system, circuit, and technology levels. In the Special Issue on Multifunctional Circuits and Systems for Future Generations of Wireless Communications, we are looking for circuits and systems solutions for multiple communication standards. Examples of topics qualifying for the special issue include: • Adaptive radio circuits and systems • Multifunctional multistandard multi-band circuits and systems • Software-defined radio circuits and systems • Cognitive radio circuits and systems • Low-voltage low-power RF and analog circuits for future generations wireless systems • Ultra Wide Band circuits and systems

Ieee transactions on circuits and systems—ii: express briefs

In recent years, wearable devices have attracted attention because of their ability to enhance the quality of life. This disruptive technology has helped healthcare professionals with intervening early in chronic diseases, especially amongst independently living patients, and has facilitated real-time monitoring of patients’ vital signs remotely. One of the major bottlenecks that hamper the adoption of wearable device is the continuous power supply. Most wearable devices solely depend on battery supply. When the energy stored in the battery is depleted, the operation of wearable devices is affected. To overcome this limitation, efficient energy harvesters for wearable devices are crucial. The paper primarily aims to present a comprehensive classification of different energy sources that can be capitalized to power wearable devices. In addition, this research paper deals with the key challenges that must be considered in the development of autonomous wearable devices for telemedicine applications with a proposed system design for wearable device that uses energy harvesting technology.

Chen-Yi Lee

Papers

A 1-GS/s FFT/IFFT processor for UWB applications

An all-digital phase-locked loop for high-speed clock generation

Design of an FFT/IFFT Processor for MIMO OFDM Systems

Ieee transactions on circuits and systems—ii: express briefs

Energy Harvesting For Wearable Devices: A Review