David M. Fried

TL;DR: In this paper, metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation, and they satisfy the following metal gate technology requirements: ideal mobility, low gate leakage, high transconductance, competitive I/sub on/I/sub off, and adjustable V/sub t/.

TL;DR: In this article, double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated and shown to have drain currents competitive with fully optimized bulk silicon technologies.

TL;DR: In this article, a test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device, in electrical contact with the probe pads, and a gate electrode structure to be tested, where the electrical contact between the first and second conductive lines and the first or more first conductive line is facilitated by a localized dielectric breakdown.

TL;DR: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region adjacent to the first region; and a first terminal including: a first deep trench located in the first regions, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first shallow trench as discussed by the authors.

TL;DR: In this paper, a method of forming a conductive spacer on a semiconductor device was proposed, which includes depositing a polysilicon layer on the semiconductor devices, selectively implanting dopant ions in the poly-silicon layers on the first side of a transistor region of the semiconductors, and then removing the poly silicon layer except for the conductive area.