Christopher L. Rexer

TL;DR: In this article, a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance.

TL;DR: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type as discussed by the authors, and each of the plurality of pillars of second conductivities type further includes an implant portion filled with semiconductor material.

TL;DR: In this paper, a monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region, where a conductor layer fills the contact opening to electrically contact.

TL;DR: In this article, a semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region, and an active trench extending through the well region and into the drift regions.

TL;DR: In this paper, a semiconductor structure which includes a trench gate FET is formed as follows: a plurality of trenches are formed in a semiconductors region using a mask, which consists of a first insulating layer over a surface of the semiconductor region, a first oxidation barrier layer over the first layer, and a second layer covering the first barrier layer.