An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Electronic devices and systems, and methods for making and using the same

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Superjunction Structures for Power Devices and Methods of Manufacture

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

Power MOSFET designs have been moving to higher performance particularly in the medium voltage area. (60V to 300V) New designs require lower specific on-resistance (R SP ) thus forcing designers to push the envelope of increasing the electric field stress on the shielding oxide, reducing the cell pitch, and increasing the epitaxial (epi) drift doping to reduce on resistance. In doing so, time dependant avalanche instabilities have become a concern for oxide charge balanced power MOSFETs. Avalanche instabilities can initiate in the active cell and/or the termination structures. These instabilities cause the avalanche breakdown to increase and/or decrease with increasing time in avalanche. They become a reliability risk when the drain to source breakdown voltage (BV dss ) degrades below the operating voltage of the application circuit. This paper will explain a mechanism for these avalanche instabilities and propose an optimum design for the charge balance region. TCAD simulation was employed to give insight to the mechanism. Finally, measured data will be presented to substantiate the theory.

Avalanche instability in oxide charge balanced power MOSFETs

In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.

Methods and apparatus related to termination regions of a semiconductor device

Termination region of a semiconductor device

In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region. A dielectric lines a bottom portion of the trench, the dielectric having a first portion disposed in the termination region of the semiconductor region and a second portion disposed in the active region of the semiconductor region, the first portion of the dielectric disposed in the termination region having a vertical thickness different than a vertical thickness of the second portion of the dielectric disposed in the active region.

Richard Stokes

Papers

Power semiconductor devices and methods of manufacture

Avalanche instability in oxide charge balanced power MOSFETs

Methods and apparatus related to termination regions of a semiconductor device

Termination region of a semiconductor device

Apparatus related to termination regions of a semiconductor device