G
G. Le Carval
Researcher at French Alternative Energies and Atomic Energy Commission
Publications - 31
Citations - 358
G. Le Carval is an academic researcher from French Alternative Energies and Atomic Energy Commission. The author has contributed to research in topics: Ballistic conduction & Monte Carlo method. The author has an hindex of 9, co-authored 31 publications receiving 339 citations. Previous affiliations of G. Le Carval include Commissariat à l'énergie atomique et aux énergies alternatives.
Papers
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Journal ArticleDOI
Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit
TL;DR: In this paper, the impact of geometrical parameters on the performance of impact ionization MOSFET (IMOS) was investigated, such as the gate length, the intrinsic length, and the Si film thickness.
Journal ArticleDOI
A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET
E. Fuchs,Philippe Dollfus,G. Le Carval,Sylvain Barraud,D. Villanueva,F. Salvetti,Herve Jaouen,Thomas Skotnicki +7 more
TL;DR: In this paper, a backscattering model suitable for compact modeling of nanoscale MOSFETs was developed within the Landauer flux-scattering theory, which is based on a careful analysis of transport in device using Monte Carlo simulation.
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Experimental determination of the channel backscattering coefficient on 10–70 nm-metal-gate Double-Gate transistors
V. Barral,Thierry Poiroux,Maud Vinet,Julie Widiez,Bernard Previtali,P. Grosgeorges,G. Le Carval,Sylvain Barraud,Jean-Luc Autran,Daniela Munteanu,Simon Deleonibus +10 more
TL;DR: In this paper, the authors presented the electrically characterized architectures and the methodology used to extract the backscattering coefficient (r SAT ) for different gate lengths (10, 20 and 70 nm) and with temperatures ranging from 100k to 290k.
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Impact of Ballistic and Quasi-Ballistic Transport on Performances of Double-Gate MOSFET-Based Circuits
TL;DR: A drift-diffusion-like formulation for including ballistic and quasi-ballistic transport in the simulation of double-gate MOSFETs has been implemented in a technology computer-aided design (TCAD) simulator as mentioned in this paper.
Journal ArticleDOI
105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers
C. Le Royer,Laurent Clavelier,Claude Tabone,K. Romanjek,Chrystel Deguet,Loic Sanchez,J.M. Hartmann,M.-C. Roure,H. Grampeix,S. Soliveres,G. Le Carval,R. Truche,A. Pouydebasque,M. Vinet,Simon Deleonibus +14 more
TL;DR: In this paper, the authors report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105nm) GeOI pMOSFETs.