Gordon K. Madson

TL;DR: In this article, a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance.

TL;DR: In this paper, a conformal oxide film is used to fill the bottom of a trench formed in a semiconductor substrate and cover a top surface of the substrate, and then the oxide film can be etched off the top surface and inside the trench to leave a substantially flat layer of oxide having a target thickness at bottom of the trench.

TL;DR: In this paper, a selective epitaxial growth (SEG) process is used to form an epitaxia layer around and over the oxide pillars, and a trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide column.

TL;DR: In this article, a semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region, and an active trench extending through the well region and into the drift regions.

TL;DR: In this paper, a gate electrode is placed in an upper portion of the trench over the inter-electrode dielectric, and a gate dielectrically lines upper trench sidewalls.