G
Guy Brammertz
Researcher at University of Hasselt
Publications - 166
Citations - 3568
Guy Brammertz is an academic researcher from University of Hasselt. The author has contributed to research in topics: Thin film & Solar cell. The author has an hindex of 30, co-authored 157 publications receiving 3175 citations. Previous affiliations of Guy Brammertz include Katholieke Universiteit Leuven & European Space Research and Technology Centre.
Papers
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Journal ArticleDOI
On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates
Koen Martens,Chi On Chui,Guy Brammertz,B. De Jaeger,Duygu Kuzum,Marc Meuris,Marc Heyns,Tejas Krishnamohan,Krishna C. Saraswat,Herman Maes,Guido Groeseneken +10 more
TL;DR: In this paper, the authors show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions, and that it is possible to both under- and overestimate the interface trap density by more than an order of magnitude.
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Characterization of defects in 9.7% efficient Cu2ZnSnSe4-CdS-ZnO solar cells
Guy Brammertz,Marie Buffiere,S. Oueslati,S. Oueslati,S. Oueslati,H. Elanzeery,H. Elanzeery,H. Elanzeery,K. Ben Messaoud,K. Ben Messaoud,K. Ben Messaoud,Sylvester Sahayaraj,Sylvester Sahayaraj,Christine Köble,Marc Meuris,Jef Poortmans +15 more
TL;DR: In this paper, the authors have fabricated Cu2ZnSnSe4-CdS-ZnO solar cells with a total area efficiency of 9.7% by selenization of sputtered Cu10Sn90, Zn, and Cu multilayers.
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Electrical study of sulfur passivated In0.53Ga0.47As MOS capacitor and transistor with ALD Al2O3 as gate insulator
TL;DR: In this article, the authors compared the interface trap distributions of sulfur treated Al. 2O"3/In"0"."5"3Ga" 0"."4"7As interfaces, which underwent MOS capacitor and transistor fabrication processes.
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Characteristic trapping lifetime and capacitance-voltage measurements of GaAs metal-oxide-semiconductor structures
Guy Brammertz,Koen Martens,Sonja Sioncke,Annelies Delabie,Matty Caymax,Marc Meuris,Marc Heyns +6 more
TL;DR: In this article, the authors show the implications of the free carrier trapping lifetime on the capacitance-voltage (CV) characterization method applied to metal-oxide-semiconductor (MOS) structures.
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A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ and InP Capacitors
TL;DR: In this paper, the authors derived the interface state densities of In0.53Ga0.47As and InP MOS devices with various high-κ dielectrics, together with the corresponding border trap density inside the highκ oxide.