J
Jack DiLullo
Researcher at IBM
Publications - 17
Citations - 481
Jack DiLullo is an academic researcher from IBM. The author has contributed to research in topics: Microprocessor & Physical design. The author has an hindex of 9, co-authored 17 publications receiving 478 citations.
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Proceedings ArticleDOI
Physical design of a fourth-generation POWER GHz microprocessor
Carl J. Anderson,John George Petrovick,J. Keaty,James D. Warnock,G. Nussbaum,J.M. Tendier,Craig R. Carter,Shao-Fu S. Chu,Joachim Gerhard Clabes,Jack DiLullo,P. E. Dudley,P. Harvey,Byron L. Krauter,J. LeBlanc,Pong-Fei Lu,Bradley McCredie,G. Plum,Phillip J. Restle,Steve Runyon,Michael R. Scheuermann,S. Schmidt,J. Wagoner,R. Weiss,S. Weitzel,B. A. Zoric +24 more
TL;DR: The fourth-generation POWER processor as discussed by the authors contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP.
Proceedings ArticleDOI
Design of the Power6 Microprocessor
Joshua Friedrich,Bradley McCredie,Norman Karl James,B. Huott,Brian W. Curran,Eric Fluhr,Gaurav Mittal,E. Chan,Y.H. Chan,Donald W. Plass,Sam Gat-Shang Chu,Hung Le,L. Clark,J. Ripley,Scott A. Taylor,Jack DiLullo,M. Lanzerotti +16 more
TL;DR: The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability.
Proceedings ArticleDOI
Design and implementation of the POWER5 microprocessor
Joachim Gerhard Clabes,Joshua Friedrich,Mark D. Sweet,Jack DiLullo,Sam Gat-Shang Chu,Donald W. Plass,James W. Dawson,Paul H. Muench,Larry Powell,Michael Stephen Floyd,Balaram Sinharoy,Mike Lee,Michael Normand Goulet,James Donald Wagoner,Nicole Schwartz,Steve Runyon,Gary Alan Gorman,Phillip J. Restle,Ronald Nick Kalla,Joseph McGill,Steve Dodson +20 more
TL;DR: POWERS offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support.
Journal ArticleDOI
IBM POWER6 microprocessor physical design and design methodology
R. Berridge,R. Averill,A. E. Barish,Michael Alexander Bowen,Peter J. Camporese,Jack DiLullo,P. E. Dudley,Joachim Keinert,David W. Lewis,R. D. Morel,Thomas Edward Rosser,Nicole Schwartz,P. Shephard,Howard H. Smith,D. Thomas,Phillip J. Restle,J. R. Ripley,Steve Runyon,Patrick M. Williams +18 more
TL;DR: Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.
Design and Implementation of the POWER5 TM Microprocessor
Joachim Gerhard Clabes,Joshua Friedrich,Mark D. Sweet,Jack DiLullo,Sam Gat-Shang Chu,Donald W. Plass,Paul D. Muench,Larry Powell,Michael Floyd,Balaram Sinharoy,Mike Lee,James Donald Wagoner,Nicole Schwartz,Steve Runyon,Gary E. Gorman,Phillip J. Restle,Ronald Nick Kalla,Joseph McGill,Steve Dodson +18 more
TL;DR: The 276M transistor processor is implemented in 130nm silicon-on-insulator technology with 8-level of Cu metallization and operates at >1.5 GHz.