Proceedings ArticleDOI
Physical design of a fourth-generation POWER GHz microprocessor
Carl J. Anderson,John George Petrovick,J. Keaty,James D. Warnock,G. Nussbaum,J.M. Tendier,Craig R. Carter,Shao-Fu S. Chu,Joachim Gerhard Clabes,Jack DiLullo,P. E. Dudley,P. Harvey,Byron L. Krauter,J. LeBlanc,Pong-Fei Lu,Bradley McCredie,G. Plum,Phillip J. Restle,Steve Runyon,Michael R. Scheuermann,S. Schmidt,J. Wagoner,R. Weiss,S. Weitzel,B. A. Zoric +24 more
- pp 232-233
TLDR
The fourth-generation POWER processor as discussed by the authors contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP.Abstract:
The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.read more
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Journal ArticleDOI
Introduction to the cell multiprocessor
TL;DR: This paper discusses the history of the project, the program objectives and challenges, the disign concept, the architecture and programming models, and the implementation of the Cell multiprocessor.
Journal ArticleDOI
Rotary traveling-wave oscillator arrays: a new clock technology
J. Wood,T.C. Edwards,Steve Lipa +2 more
TL;DR: The rotary traveling-wave oscillators (RTWOs) as mentioned in this paper represent a new transmission-line approach to gigahertz-rate clock generation, which operates by creating a rotating traveling wave within a closed-loop differential transmission line.
Journal ArticleDOI
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
D. Pham,T. Aipperspach,David William Boerstler,M. Bolliger,Rajat Chaudhry,D. Cox,P. Harvey,Paul Marlan Harvey,Harm Peter Hofstee,Charles Ray Johns,J. Kahle,Atsushi Kameyama,J. Keaty,Y. Masubuchi,Mydung Pham,J. Pille,S. Posluszny,Mack W. Riley,Daniel Lawrence Stasiak,Masakazu Suzuoki,Osamu Takahashi,James D. Warnock,S. Weitzel,D. Wendel,Kazuaki Yazawa +24 more
TL;DR: In this paper, the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends, are reviewed, and a first-generation Cell processor is described.
Journal ArticleDOI
SOI technology for the GHz era
TL;DR: The reasons for performance improvement with SOI, and its scalability to the 0.1-µm generation and beyond are described, which is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.
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Electronic Design Automation: Synthesis, Verification, and Test
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
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