Showing papers by "Jan Craninckx published in 2012"

A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

Abstract: A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC in 40 nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR with a total of two bits of redundancy. Calibration is leveraged to adjust the uncertain gain of the chosen residue amplifier and various other non-idealities. The ADC achieves a peak SNDR of 62 dB at 10 MS/s, and 56 dB for a Nyquist input at 250 MS/s. The low frequency energy per conversion step ranges from 7 fJ at 10 MS/s to 10 fJ at 250 MS/s.

A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS

Abstract: A successive approximation analog-to-digital converter (ADC) architecture is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. While targeting medium resolutions and speed, the threshold configuring (TC) ADC achieves low power consumption and small area occupation by using a fully dynamic configurable comparator and an asynchronous controller, with no need for a highly linear feedback D/A converter. The TC-ADC embeds its own references, and relies on a minimal amount of passive components or calibration loops. A 6-bit prototype implementation in 90-nm digital CMOS technology achieves 32-dB SNDR at 50 MS/s and consumes 240 μW from 1-V analog and 0.7-V digital supplies. This results in 150 fJ/conversion-step in a core area occupation of only 0.0055 mm .

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass $\Delta\Sigma$ Modulator and Polyphase Decimation Filter

Abstract: A fourth-order continuous-time RF bandpass ΔΣ ADC has been fabricated in 40 nm CMOS for fs/4 operation around a 2.22 GHz central frequency. A complete system has been implemented on the test chip including the ADC core, the fractional-N PLL with clock generation network, and the digital decimation filters and downconversion (DFD). The quantizers of the ADC are six times interleaved enabling a polyphase structure for the DFD and relaxing clock frequency requirements. This quantization scheme realizes a sampling rate of 8.88 GS/s which is the highest sampling speed for RF bandpass ΔΣ ADCs reported in standard CMOS to date enabling high oversampling ratios for RF digitization without compromising power-efficient implementation of the DFD. Measurements show that the ADC achieves a dynamic range of 48 dB in a band of 80 MHz with an IIP3 of 1 dBm.

A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range

Abstract: A charge-domain SAR ADC is presented which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors as sampling capacitor for passive amplification to relax the comparator noise requirements without compromising linearity. The prototype in 40 nm low power CMOS process consists of a 1.1-17.6 mS transconductor, combined with a 10 b 0-80 MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45 mA from a 1.1 V supply and achieves a peak SNDR of 56.85 dB at 40 MS/s.

A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors

Abstract: This paper presents a new approach to increase the output power and to enhance the drain efficiency of Direct Digital RF Modulators (DDRM). Two differential four-phase DDRMs are organized in a Doherty-like configuration using two different transformers. The modulated tuning capacitors concept is proposed to achieve a high efficiency at maximum output power and at back-off. To demonstrate this principle, a 2 GHz IQ Digital Doherty Transmitter with on-chip transformers has been integrated in 90 nm CMOS Technology. The digital IQ transmitter achieves a maximum output power of 24.8 dBm with 26% drain efficiency and 26% drain efficiency at 6 dB back-off. With a 10 MHz RFBW multi-tone OFDM signal, the transmitter consumes 176 mA from a 2.4 V supply. It achieves 18.8 dBm RMS output power with 18% average drain efficiency.

CMOS software-defined radio transceivers: Analog design in digital technology

Abstract: The introduction of several new cellular and connectivity radio standards has attracted the wireless industry to the concept of softwaredefined radio systems, preferably implemented in advanced nanometer CMOS technology. Several novel circuits and architectures have been investigated to cope with the huge design challenges involved, an overview of which will be given in this article. First, two digitally inspired receiver approaches are presented in detail. Discrete-time radio receivers exploit the paradigm that time is better controllable than voltage in modern CMOS, and are implemented using transistors mainly as switches. RF ADCs digitize the signal as close as possible to the antenna, but still require highspeed analog circuits to achieve the required performance. The second part of the article presents a "traditional" direct-conversion architecture, including also a transmitter, where several new circuits and architectures are used to exploit as much as possible the capabilities of a modern digital CMOS technology.

Design of an intrinsically-linear double-VCO-based ADC with 2 nd -order noise shaping

Abstract: This paper presents the modeling and design consideration of a time-based ADC architecture that uses VCOs in a high-linearity, 2nd-order noise-shaping delta-sigma ADC. Instead of driving the VCO by a continuous analog signal, which suffers from the nonlinearity problem of the VCO gain, the VCO is driven in an intrinsically linear way, by a time-domain PWM signal. The two discrete levels of the PWM waveform define only two operating points of the VCO, therefore guaranteeing linearity. In addition, the phase quantization error between two consecutive samples is generated by a phase detector and processed by a second VCO. Together with the output of the first VCO, a MASH 1-1 2nd-order noise-shaping VCO-based time-domain delta-sigma converter is obtained. Fabricated in 90nm CMOS technology, the SFDR is larger than 67dB without any calibration for a 20MHz bandwidth.

Spatially oversampled TDC with digital resolution enhancement

Abstract: A digital resolution enhancement technique for time-to-digital converters (TDC) is proposed. This involves a simultaneous multi-channel measurement of a time interval with low complexity TDC of varying low resolutions. The coarse outputs of each converter are digitally post-processed to obtain an output whose precision is much better than that of the individual converters. Three post-processing algorithms are proposed and their limitations in presence of converter non-idealities are analyzed. A prototype system with 8 channels is implemented in 90 nm CMOS. 40MS/s output of each channel is algorithmically combined to obtain over 2.2---3X measured improvement in the resolution in 4/6/8 channel modes, validating the system principle. The chip occupies 0.3 mm2 and draws up to a maximum of 4 mA from a 1.2 V supply.

Low-Power Successive Approximation ADCS for Wireless Applications

Abstract: This chapter discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8–10 bit and a few 10’s of MHz sampling speed. An overview is given of recent techniques that reduce the switching power in the capacitive DAC, and as such improve the power efficiency of the ADC up to levels that are out of reach of the typically used pipeline architecture.