Showing papers by "Jose Silva-Martinez published in 2017"

Low-Power ${G}_{{m}}{-}C$ Filter Employing Current-Reuse Differential Difference Amplifiers

Abstract: This paper deals with the design of low-power high-performance continuous-time filters. The proposed operational transconductance amplifier architecture employs current-reuse differential difference amplifiers in order to produce more power-efficient ${G}_{{m}}{-}{C}$ filter solutions. To demonstrate this, a sixth-order low-pass Butterworth filter was designed in a 0.18- $\mu\text{m}$ CMOS, achieving a 65-MHz −3-dB frequency, an in-band input-referred third-order intercept point of 12 dBm, and an input-referred noise density of 40 nV/Hz1/2, while only consuming 8.07 mW from a 1.8-V supply and occupying a total chip area of 0.21 mm2 with a power consumption of only 1.19 mW per pole.

A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS

Abstract: This paper proposes a multistage noise-shaping continuous-time sigma-delta modulator (CT $\Sigma \Delta \text{M}$ ) with on-chip RC time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise-cancellation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CT $\Sigma \Delta \text{M}$ stages, each of which consists of an integrator-based active- RC loop filter, current-steering feedback digital-to-analog converters, and a 4-b flash quantizer. On-chip RC time constant calibration circuits and high-gain multistage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to: 1) synthesize a fourth-order noise transfer function with dc zeros; 2) simplify the design of NCF; and 3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40-nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise-and-distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power consumption (P) from 1.1/1.15/2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as $\text {FOM}=\text {SNDR}+10\times \log _{10}(\text {BW}/\text {P})$ , is 165.1 dB.

A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques

Abstract: This paper presents a high-performance digitizer based on column-parallel single-slope analog-to-digital converter (SS-ADC) topology for readout of a back-illuminated 3-D-stacked CMOS image sensor. To address the high power consumption issue in high speed digital counters, a passing window (PW)-based hybrid counter topology is proposed. In this approach, the memory cells in the digital counters of SS-ADCs are disconnected from the global bus during non-relevant timing. To address the high column fixed pattern noise (FPN) under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. In this technique, the AZ process is employed twice at reset and signal level, respectively. The double AZ scheme not only allows the comparator to serve as a crossing detector around the common-mode level, but it also enables low-voltage comparator design. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column FPN of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling. A single-column digitizer consumes a total power of 66.8 $\mu \text{W}$ and occupies an area of 5.4 $\mu \text{m} \times $ 610 $\mu \text{m}$ .

A Wideband Low-Power-Consumption 22–32.5-GHz 0.18- $\mu \text{m}$ BiCMOS Active Balun-LNA With IM2 Cancellation Using a Transformer-Coupled Cascode-Cascade Topology

Abstract: A low-power-consumption wideband 0.18- $\mu \text{m}$ BiCMOS active balun-low noise amplifier (LNA) with linearity improvement technique for millimeter-wave applications is proposed. The linearity technique utilizes constant Gm transconductance structure with the second-order intermodulation (IM2) cancellation that provides robustness to input and output variations. The constant Gm is established with equal emitters’ area ratios and proper base-emitter biasing voltage, thus improving linearity. Furthermore, power saving is achieved using inductive coupling boosting the overall Gm structure and reducing the current consumption for the auxiliary gain stage. The measured balun-LNA’s power gain between the input and two outputs is 15.4 and 15.6 dB with input return loss greater than 8.7 dB. The gain and phase mismatches are less than 1.8 dB and 12°, respectively. The balun-LNA noise figures between the input and two outputs are less than 5.5 and 6 dB at 32.5 GHz. The measured input points [referred 1-dB gain compressions ( $P_{\mathrm {{in}}}1$ dB’s), input referred third-order intercept IIP3’s] and the input referred second-order intercept points (IIP2’s) are more than −14.6, −5.7, and 42 dBm across 22–32.5 GHz, respectively, and the total power consumption is less than 9 mW drawn from 1.8 V power supply.

A 75-MHz Continuous-Time Sigma–Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage

Abstract: A wide-bandwidth (BW) power-efficient continuous-time ΣΔ modulator (CTΣΔM) is presented. The modulator introduces a third-order filter implemented with a lossless integrator and a multiple-feedback single-amplifier biquadratic filter with embedded loop stability compensation. An active summing block is implemented by employing a common-gate current buffer followed by a transimpedance amplifier. This combination relaxes the specification requirements of the operational amplifier by making its required BW independent of the closed-loop gain. The proposed technique achieves optimum BW with reduced power consumption, making it functional for over gigahertz operation. Fabricated in a standard 40-nm CMOS technology, and clocked at 3.2 GHz, the CTΣΔM achieves a signal-to-noise-and-distortion ratio of 65.5 dB over 75-MHz BW while consuming 22.8 mW of power. The obtained Walden's figure of merits is 98 fJ/conv-step.

Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices

Abstract: Level crossing sampling (LCS) is a power-efficient analog-to-digital conversion scheme for spikelike signals that arise in many Internet of Things-enabled automotive and environmental monitoring applications. However, LCS scheme requires a dedicated time-to-digital converter with large dynamic range specifications. In this paper, we present a compressed LCS that exploits the signal sparsity in the time domain. At the compressed sampling stage, a continuous-time ternary encoding scheme converts the amplitude variations into a ternary timing signal that is captured in a digital random sampler. At the reconstruction stage, a low-complexity split-projection least squares (SPLSs) signal reconstruction algorithm is presented. The SPLS splits random projections and utilizes a standard least squares approach that exploits the ternary-valued amplitude distribution. The SPLS algorithm is hardware friendly, can be run in parallel, and incorporates a low-cost k-term approximation scheme for matrix inversion. The SPLS hardware is analyzed, designed, and implemented in FPGA, achieving the highest data throughput and the power efficiency compared with the prior arts. Simulations of the proposed sampler in an automotive collision warning system demonstrate that the proposed compressed LCS can be very power efficient and robust to wireless interference, while achieving an approximately eightfold data volume compression when compared with Nyquist sampling approaches.

Algorithmic-pipelined ADC with a modified residue curve for better linearity

Abstract: In this paper, the minimum total required transconductance for the different architectures of the pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. It is shown that the Algorithmic-Pipelined ADC requires a simpler Sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the Algorithmic-Pipelined architecture is more-tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals.

A 13bit 200MS/S pipeline ADC with current-mode MDACs

Abstract: A 13bit 200MS/s pipeline ADC with current-mode MDAC is implemented in this work. Compared with a conventional MDAC architecture, the proposed current mode MDAC reduces power consumption for the residual amplifier between two pipelined stages. The fabricated ADC achieves a 58.4dB / 57.6dB SNDR and a 75dB / 72dB SFDR for a sinusoidal input at 4.15MHz / 97.9MHz respectively. The power consumption of the ADC operating at 200MS/s is 8.4mW and the conversion FoM is 64fJ/conv-step. The prototype occupies an active area of 0.23mm2 in a 40nm CMOS technology.

A 200MSPS time-interleaved 12-bit ADC system with digital calibration

Abstract: This paper proposes a time interleaved ADC architecture employing a digital background calibration technique based on evolutionary-computation The algorithm iteratively minimizes an error function (EF) which models the gain, offset and timing mismatches between the ADC channels The system was implemented using off-the-shelf Analog to Digital Converters (ADCs) and a Field Programmable Gate Array (FPGA) Experimental results demonstrate that the proposed calibration technique allows an SNDR improvement of 26dB for just 32 iterations of calibration

Blocker-Tolerant and High-Sensitivity $\Delta \Sigma $ Correlation Digitizer for Radar and Coherent Receiver Applications

Abstract: In this paper, a coherent subsampling digitizer for pulsed Doppler radar systems is proposed. Prior to transmission, the radar system modulates the RF pulse with a known pseudorandom binary phase shift keying (BPSK) sequence. Upon reception, the radar digitizer uses a programmable sample-and-hold circuit to multiply the received waveform by a properly time-delayed version of the known a priori BPSK sequence. This operation demodulates the desired echo signal while suppressing the spectrum of all in-band noncorrelated interferers, making them appear as noise in the frequency domain. The resulting demodulated narrowband Doppler waveform is then subsampled at the IF frequency by a delta–sigma modulator. Because the digitization bandwidth within the delta–sigma feedback loop is much less than the input bandwidth to the digitizer, the thermal noise outside of the Doppler bandwidth is effectively filtered prior to quantization, providing an increase in signal-to-noise ratio (SNR) at the digitizer’s output compared with the input SNR. In this demonstration, a delta–sigma correlation digitizer is fabricated in a 0.18- $\mu \text{m}$ CMOS technology. The digitizer has a power consumption of 1.12 mW with an IIP3 of 7.5 dBm. The digitizer is able to recover Doppler tones in the presence of blockers up to 40 dBm greater than the Doppler tone.

High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications

Abstract: This paper focuses on the design and analysis of multi-stage noise-shaping (MASH) sigma-delta modulators. Fundamentals and properties of MASH modulators are discussed. A detailed methodology on analyzing continuous-time MASH (CT-MASH) modulator based on the impulse invariant transformation is also described. Two fabricated design examples are discussed: a 130 nm CMOS CT-MASH 4-0 employing a digital pseudo-MASH compensation consumes 20mW and achieves 75 dB peak SNDR over a 15 MHz bandwidth with an active area of 1.3 mm2; a 40 nm CMOS CT-MASH 2-2 architecture achieves peak SNDR of 74.4 dB within the signal bandwidth of 50.3 MHz with power consumption of 43.0 mW and active area of 0.265 mm2.

Multitone ACLR and Its Applications to Linear PA Design

Abstract: Analysis and measurements results of a multitone frequency spectrum leakage have shown results comparable to those of modulated signals with a similar peak-to-average power ratio. In this brief, the adjacent channel leakage ratio of multitone signals is analyzed, and it is shown that the closed-form result is related to third-order intermodulation distortion that can be obtained by a two-tone test. Such a correlation enables a rough prediction of an RF power amplifier’s (PA) linearity performance through a simple and fast simulation of a two-tone test, thereby shortening the design time. The theoretical analysis is experimentally demonstrated by employing a 1.9-GHz PA fabricated in 40-nm CMOS technology.