Juan Pablo Duarte

TL;DR: In this article, a unified compact model for carrier transport from the drift-diffusion to the ballistic regime is presented, which accounts for carrier degeneracy effects in ballistic transport and is implemented into the industry standard compact models for FinFETs, fully depleted silicon-on-insulator (FDSOI) devices and bulk MOSFET.

TL;DR: In this paper, the authors present a compact model for source-to-drain tunneling current in sub-10nm gate-all-around FinFETs, which analytically captures the dependence on biases in the tunneling probability expression.

TL;DR: In this paper, the authors investigated the thermal resistance of FinFETs with the variation in the number of fin, shape of fin and fin pitch, and proposed a model for thermal resistance behavior correctly with N fin and F pitch variation.

TL;DR: A Monte Carlo TCAD simulation study of the impact of polycrystallinity and dielectric phases of the ferroelectric film on an 8/7 nm node NC-FinFET is presented in this paper.

TL;DR: In this paper, the back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed.