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Journal ArticleDOI

Modeling of nonlinear thermal resistance in FinFETs

14 Mar 2016-Japanese Journal of Applied Physics (IOP Publishing)-Vol. 55, Iss: 4, pp 1-5
Abstract: In this paper, self-consistent three-dimensional (3D) device simulations for exact analysis of thermal transport in FinFETs are performed. We analyze the temperature rise in FinFET devices with the variation in the number of fins (N fin), shape of fins and fin pitch (F pitch). We investigate that the thermal resistance R th has nonlinear dependency on N fin and F pitch. We formulate a model for thermal resistance behavior correctly with N fin and F pitch variation. The proposed formulation is implemented in industry standard Berkeley short-channel independent gate FET model for common multi-gate transistors (BSIM-CMG) and validated with both experimental data and TCAD simulations.

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Topics: Fin (59%), Thermal resistance (53%)
Citations
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Journal ArticleDOI
Abstract: In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.

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12 citations


Journal ArticleDOI
Abstract: ZnO thin films were synthesized using sol–gel method at 0.25 and 0.5 M molarity concentration. Moreover, the obtained thin films were Calcium-doped with 1 and 5 at% concentration. In order to investigate the structural changes in the molecular binding between ZnO and Ca, Fourier Transform Infrared spectroscopy (FTIR), Micro-Raman Spectroscopy and X-ray diffraction (XRD) were performed. The surface morphology and the chemical constituents distribution of the films were studied through Scanning Electron Microscopy (SEM), energy-dispersive X-ray spectroscopy (EDX) and Atomic Force Microscopy (AFM), respectively. The optical and electrical properties were studied by UV–Vis spectroscopy, Spectral ellipsometry and electrical I–V measurements. The results show that the properties of prepared ZnO thin films were strongly influenced by the molarity concentration and Ca-dopant. The band shape obtained at FTIR is a band attributable to metal oxide bonds and can be attributed to the vibrational assignment of Zn–O bond. SEM-EDX and AFM investigations reveal an enlarged surface area due to the porous nature of the thin films and confirm the presence of Ca in the ZnO matrix. The XRD and Raman analyses indicate the achievement of the high crystalline quality and confirm the wurtzite phase of the synthesized thin films. The films transmittance spectra indicate values between 81 and 93% in the 350–800 nm wavelength region. We further performed I–V characteristics, resulting that Ca has a different impact of the electrical performances.

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12 citations


Journal ArticleDOI
Abstract: The localized thermal effect caused by the self-heating effect (SE) becomes important for nanoscale 3-D transistors such as bulk FinFET because the thermal coupling from substrate is critical in such 3-D transistors. In this brief, we analyze the SE in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors. We systematically analyze the impact of key device parameters of bulk FinFET in view of the SE. Since the SE affects performance and reliability of transistors simultaneously, we define new figures of merit including ac delay and bias temperature instability for the first time, and it is found that the proper source/drain contact scheme design can achieve performance and reliability improvement at the same time in 5-nm bulk FinFET technology.

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8 citations


Journal ArticleDOI
TL;DR: The impact of self-heating effect (SHE) in hybrid FinFET, which is a promising device for high-performance applications, is presented and the linear dependence of thermal resistance (Rth) on Lg, Wfin, and tbox; and nonlinear dependence on Lpitch and N is studied.

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Abstract: In this paper, we presented the impact of self-heating effect (SHE) in hybrid FinFET, which is a promising device for high-performance applications. The impact of variation of channel length (Lg), fin width (Wfin), buried oxide thickness (tbox), the pitch of the device (Lpitch) and a number of fins (N) on the increase in lattice temperature for hybrid FinFET is observed. The linear dependence of thermal resistance (Rth) on Lg, Wfin, and tbox; and nonlinear dependence on Lpitch and N is studied. It is seen that unlike trigate FinFET, hybrid FinFET have the advantage of increased drain current from 50 μA to 103 μA with an increase in Lpitch from 50 nm to 250 nm, also reduces lattice temperature from 726.5 K to 495.6 K.

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6 citations


Journal ArticleDOI
Abstract: Silicon-Nanotube-based ultra-thin DGAA MOSFETs have been extensively studied for their superior immunity to short channel effects (SCEs) and better drive current capability; however, the reliability issues owing to self-heating effects (SHEs) and hot carrier injection (HCI) degradation are yet to be investigated systematically. In advanced non-planar device structures, an increase in power density due to ultra-scaled device dimensions can aggravate both the carrier heating as well as lattice heating. In this paper, 3-dimensional (3-D) electrothermal (ET) simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermal behavior and SHEs in ultra-thin DGAA MOSFET. 3-D TCAD simulation parameters are calibrated with the data obtained from the literature. Through advanced 3-D ET simulations, we demonstrate that the device thermal contact resistance adversely influences both the carrier temperature as well as lattice temperature. The implication of SHE on the device output drive current reduction is also analyzed. The effective drive current method is used to observe the impact of SHE on the intrinsic delay of the device. Further, the performance of the device due to HCI is also highlighted. HCI significantly degrades the overall device performance leading to increased gate leakage current. Finally, the reliability issues induced by SHEs with on-chip ambient temperature variations have also been interpreted using Sentauras based TCAD simulator.

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4 citations


Cites background from "Modeling of nonlinear thermal resis..."

  • ...because of the low thermal conductivity of the gate oxide material, spacer region material, and thermal contact resistance (Rth) values [15]–[16]....

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References
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Journal ArticleDOI
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638 citations


Proceedings ArticleDOI
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12 Jun 2012-
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637 citations


Journal ArticleDOI
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528 citations


Journal ArticleDOI
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324 citations


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