Modeling of nonlinear thermal resistance in FinFETs

Abstract: In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.

Abstract: ZnO thin films were synthesized using sol–gel method at 0.25 and 0.5 M molarity concentration. Moreover, the obtained thin films were Calcium-doped with 1 and 5 at% concentration. In order to investigate the structural changes in the molecular binding between ZnO and Ca, Fourier Transform Infrared spectroscopy (FTIR), Micro-Raman Spectroscopy and X-ray diffraction (XRD) were performed. The surface morphology and the chemical constituents distribution of the films were studied through Scanning Electron Microscopy (SEM), energy-dispersive X-ray spectroscopy (EDX) and Atomic Force Microscopy (AFM), respectively. The optical and electrical properties were studied by UV–Vis spectroscopy, Spectral ellipsometry and electrical I–V measurements. The results show that the properties of prepared ZnO thin films were strongly influenced by the molarity concentration and Ca-dopant. The band shape obtained at FTIR is a band attributable to metal oxide bonds and can be attributed to the vibrational assignment of Zn–O bond. SEM-EDX and AFM investigations reveal an enlarged surface area due to the porous nature of the thin films and confirm the presence of Ca in the ZnO matrix. The XRD and Raman analyses indicate the achievement of the high crystalline quality and confirm the wurtzite phase of the synthesized thin films. The films transmittance spectra indicate values between 81 and 93% in the 350–800 nm wavelength region. We further performed I–V characteristics, resulting that Ca has a different impact of the electrical performances.

Abstract: The localized thermal effect caused by the self-heating effect (SE) becomes important for nanoscale 3-D transistors such as bulk FinFET because the thermal coupling from substrate is critical in such 3-D transistors. In this brief, we analyze the SE in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors. We systematically analyze the impact of key device parameters of bulk FinFET in view of the SE. Since the SE affects performance and reliability of transistors simultaneously, we define new figures of merit including ac delay and bias temperature instability for the first time, and it is found that the proper source/drain contact scheme design can achieve performance and reliability improvement at the same time in 5-nm bulk FinFET technology.

Abstract: In this paper, we presented the impact of self-heating effect (SHE) in hybrid FinFET, which is a promising device for high-performance applications. The impact of variation of channel length (Lg), fin width (Wfin), buried oxide thickness (tbox), the pitch of the device (Lpitch) and a number of fins (N) on the increase in lattice temperature for hybrid FinFET is observed. The linear dependence of thermal resistance (Rth) on Lg, Wfin, and tbox; and nonlinear dependence on Lpitch and N is studied. It is seen that unlike trigate FinFET, hybrid FinFET have the advantage of increased drain current from 50 μA to 103 μA with an increase in Lpitch from 50 nm to 250 nm, also reduces lattice temperature from 726.5 K to 495.6 K.

Abstract: Silicon-Nanotube-based ultra-thin DGAA MOSFETs have been extensively studied for their superior immunity to short channel effects (SCEs) and better drive current capability; however, the reliability issues owing to self-heating effects (SHEs) and hot carrier injection (HCI) degradation are yet to be investigated systematically. In advanced non-planar device structures, an increase in power density due to ultra-scaled device dimensions can aggravate both the carrier heating as well as lattice heating. In this paper, 3-dimensional (3-D) electrothermal (ET) simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermal behavior and SHEs in ultra-thin DGAA MOSFET. 3-D TCAD simulation parameters are calibrated with the data obtained from the literature. Through advanced 3-D ET simulations, we demonstrate that the device thermal contact resistance adversely influences both the carrier temperature as well as lattice temperature. The implication of SHE on the device output drive current reduction is also analyzed. The effective drive current method is used to observe the impact of SHE on the intrinsic delay of the device. Further, the performance of the device due to HCI is also highlighted. HCI significantly degrades the overall device performance leading to increased gate leakage current. Finally, the reliability issues induced by SHEs with on-chip ambient temperature variations have also been interpreted using Sentauras based TCAD simulator.

Abstract: The first physics-based analytical model is presented that unifies the descriptions of majority and minority carrier mobility and that includes screening of the impurities by charge carriers, electron-hole scattering, clustering of impurities and the full temperature dependence of both majority and minority carrier mobility Using this model, excellent agreement is obtained with published experimental data on Si The model is especially suited for device simulation purposes, because the carrier mobility is given as an analytical function of the donor, acceptor, electron and hole concentrations and of the temperature

Abstract: A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >

Abstract: A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.

Abstract: The drift velocity of electrons and holes in silicon has been measured in a large range of the electric fields (from 3 . 102to 6 . 104V/cm) at temperatures up to 430 K. The experimental data have been fitted with a simple formula for the temperatures of interest. The mean square deviation was in all cases less than 3.8 percent. A more general formula has also been derived which allows to obtain by extrapolation drift velocity data at any temperature and electric field.

Abstract: Temperature fields in microdevices made from silicon-on-insulator (SOI) wafers are strongly influenced by the lateral thermal conductivity of the silicon overlayer, which is diminished by phonon scattering on the layer boundaries. This study measures the thermal conductivity of single-crystal silicon layers in SOI substrates at temperatures between 20 and 320 K using Joule heating and electrical-resistance thermometry in microfabricated structures. Data for layers of thickness between 0.4 and 1.6 μm demonstrate the large reduction resulting from phonon-boundary scattering, particularly at low temperatures, and are consistent with predictions based on the phonon Boltzmann transport equation.