J
Juan Pablo Duarte
Researcher at University of California, Berkeley
Publications - 55
Citations - 2414
Juan Pablo Duarte is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: BSIM & MOSFET. The author has an hindex of 23, co-authored 55 publications receiving 1965 citations. Previous affiliations of Juan Pablo Duarte include KAIST.
Papers
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Proceedings ArticleDOI
Response Speed of Negative Capacitance FinFETs
Daewoong Kwon,Yu-Hung Liao,Yen-Kai Lin,Juan Pablo Duarte,Korok Chatterjee,Ava J. Tan,Ajay K. Yadav,Chenming Hu,Zoran Krivokapic,Sayeef Salahuddin +9 more
TL;DR: In this paper, the authors report on the measurement of a 101-stage ring oscillator (RO) consisting of 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance.
Journal ArticleDOI
Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor
Ming-Yen Kao,Angada B. Sachid,Yen-Kai Lin,Yu-Hung Liao,Harshit Agarwal,Pragya Kushwaha,Juan Pablo Duarte,Huan-Lin Chang,Sayeef Salahuddin,Chenming Hu +9 more
TL;DR: In this article, a new scheme was proposed to consider the dielectric (DE) phases inside polycrystalline ferroelectric (FE) materials, and a Sentaurus TCAD structure was constructed with the extracted parameters, and the simulated P-E curve was in a good agreement with the experimental data.
BSIM-CMG 108.0.0: Multi-gate MOSFET compact model: technical manual
Sourabh Khandelwal,Juan Pablo Duarte,Sriramkumar Venugopalan,Navid Paydavosi,Darsen D. Lu,Chung-Hsun Lin,Mohan Dunga,Shijing Yao,Tanvir Morshed,Ali M. Niknejad,Chenming Hu +10 more
Proceedings ArticleDOI
Recent enhancements in BSIM6 bulk MOSFET model
Harshit Agarwal,Sriramkumar Venugopalan,Maria-Anna Chalkiadaki,Navid Paydavosi,Juan Pablo Duarte,Shantanu Agnihotri,Chandan Yadav,Pragya Kushwaha,Yogesh Singh Chauhan,Christian Enz,Ali M. Niknejad,Chenming Hu +11 more
TL;DR: In this paper, the authors discuss the recent enhancements made in the BSIM6 bulk MOSFET model and validate symmetry of the model by performing Gummel Symmetry Test (GST) in DC and symmetry test for capacitances in AC.
Journal ArticleDOI
NCFET Design Considering Maximum Interface Electric Field
Harshit Agarwal,Pragya Kushwaha,Yen-Kai Lin,Ming-Yen Kao,Yu-Hung Liao,Juan Pablo Duarte,Sayeef Salahuddin,Chenming Hu +7 more
TL;DR: Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better results.