S
S. Wang
Researcher at Katholieke Universiteit Leuven
Publications - 16
Citations - 210
S. Wang is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Engineering & Computer science. The author has an hindex of 6, co-authored 11 publications receiving 145 citations.
Papers
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Journal ArticleDOI
An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III–V NMOS
Richard Kenneth Oxland,S. W. Chang,Xu Li,S. Wang,Gokul Radhakrishnan,W. Priyantha,M.J.H. van Dal,C. H. Hsieh,Georgios Vellianitis,Gerben Doornbos,Krishna Kumar Bhuwalka,Blandine Duriez,Iain G. Thayne,Ravindranath Droopad,Matthias Passlack,Carlos H. Diaz,Y. C. Sun +16 more
TL;DR: In this paper, an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance is presented.
Proceedings ArticleDOI
InAs N-MOSFETs with record performance of I on = 600 μA/μm at I off = 100 nA/μm (V d = 0.5 V)
S. W. Chang,Xu Li,Richard Kenneth Oxland,S. Wang,Chien-Hsun Wang,R. Contreras-Guerrero,Krishna Kumar Bhuwalka,Gerben Doornbos,T. Vasen,Martin Christopher Holland,Georgios Vellianitis,M.J.H. van Dal,Blandine Duriez,M. Edirisooriya,J.S. Rojas-Ramirez,Peter Ramvall,Stephen Thoms,Uthayasankaran Peralagu,C. H. Hsieh,Chang Yen-An,K. M. Yin,Erik Lind,L.-E. Wernersson,Ravindranath Droopad,I.G. Thayne,Matthias Passlack,Carlos H. Diaz +26 more
TL;DR: In this article, a record setting III-V N-MOSFET with 10 nm unstrained InAs surface channel and Lg = 130 nm operating at 0.5 V, on-current as high as Ion = 601 μA/μm (at fixed Ioff = 100 nA/m) is achieved.
Proceedings ArticleDOI
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
S. Subramanian,Maryamsadat Hosseini,Thomas Chiarella,S. Sarkar,P. Schuddinck,Boon Teik Chan,D. Radisic,G. Mannaert,Andriy Hikavyy,Erik Rosseel,Farid Sebaai,Antony Premkumar Peter,T. Hopf,P. Morin,S. Wang,Katia Devriendt,D. Batuk,G. T. Martinez,Anabela Veloso,E. Dentoni Litta,Sylvain Baudot,Yong Kong Siew,X. Zhou,B. Briggs,E. Capogreco,J. Hung,R. Koret,Alessio Spessot,Julien Ryckaert,Steven Demuynck,Naoto Horiguchi,Juergen Boemmels +31 more
TL;DR: This paper reports the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform and demonstrates functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices.
Proceedings ArticleDOI
InAs nanowire GAA n-MOSFETs with 12–15 nm diameter
T. Vasen,Peter Ramvall,Aryan Afzalian,Claes Thelander,Kimberly A. Dick,M. Holland,G. Doornbos,S. Wang,Richard Kenneth Oxland,Georgios Vellianitis,M.J.H. van Dal,Blandine Duriez,J.-R. Ramirez,Ravi Droopad,L.-E. Wernersson,Lars Samuelson,Tung-Tsun Chen,Yee-Chia Yeo,M. Passlack +18 more
TL;DR: In this paper, a gate-all-around (GAA) MOSFET with diameter d = 12-15 nm and gate-and-slot (GAS) InAs nanowires (NW) grown by MOCVD were demonstrated.
Journal ArticleDOI
Field-Effect Mobility of InAs Surface Channel nMOSFET With Low $D_{\rm it}$ Scaled Gate-Stack
S. Wang,Timothy Vasen,Gerben Doornbos,Richard Kenneth Oxland,Shang-Wen Chang,Xu Li,R. Contreras-Guerrero,Martin Christopher Holland,Chien-Hsun Wang,M. Edirisooriya,J.S. Rojas-Ramirez,Peter Ramvall,Stephen Thoms,Douglas Macintyre,Georgios Vellianitis,Gordon C. H. Hsieh,Yang-Sih Chang,Kaimin M. Yin,Yee-Chia Yeo,Carlos H. Diaz,Ravi Droopad,Iain G. Thayne,Matthias Passlack +22 more
TL;DR: In this article, the authors have investigated the characteristics of low interface state density on n-InAs with gate-stacks on nMOSFETs with gate length, channel thickness, and equivalent oxide thickness.