An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Radio-frequency identification (RFID) is a wireless data capturing technique that utilizes radio frequency (RF) waves for automatic identification of objects. RFID relies on RF waves for data transmission between the data carrying device, called the RFID tag, and the interrogator.

Chipless RFID: Bar Code of the Future

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing t...

Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum2 cell size, containing >1.9 billion transistors.

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

Interconnect process features are described for a 32nm high performance logic technology. Lower-k, yet highly manufacturable, Carbon-Doped Oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever lower metal line capacitance. The pitches have been aggressively scaled to meet the expectation for density, and the metal resistance and electromigration performance have been carefully balanced to meet the high reliability requirements while maintaining the lowest possible resistance. A new patterning scheme has been used to limit any patterning damage to the lower-k ILD and address the increasingly difficult problem of via-to-metal shorting at these very tight pitches. The interconnect stack has a thick Metal-9 layer to provide a low resistance path for the power and I/O routing that has been carefully scaled to maintain a low resistance. The combined interconnect stack provides high density, performance, and reliability, and supports a Pb-free 32nm process.

Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing

An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.

On-chip capacitors and methods of assembling same

A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

Michael A. Childs

Papers

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing

On-chip capacitors and methods of assembling same

Avd hardmask for damascene patterning