Proceedings ArticleDOI
A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array
Sanjay Natarajan,Mark Armstrong,M. Bost,Ruth A. Brain,Mark R. Brazier,C.-H. Chang,V. Chikarmane,Michael A. Childs,H. Deshpande,K. Dev,G. Ding,Tahir Ghani,Oleg Golonzka,W. Han,Jun He,R. Heussner,Robert James,I. Jin,C. Kenyon,S. Klopcic,Seung Hwan Lee,Mark Y. Liu,S. Lodha,B. McFadden,Anand Portland Murthy,L. Neiberg,J. Neirynck,Paul A. Packan,S. Pae,C. Parker,C. Pelto,L. Pipes,J. Sebastian,J. Seiple,Sell Bernhard,Swaminathan Sivakumar,B. Song,K. Tone,T. Troeger,Cory E. Weber,M. Yang,Yeoh Andrew W,Kevin Zhang +42 more
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TLDR
In this paper, a 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques.Abstract:
A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum2 cell size, containing >1.9 billion transistors.read more
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Proceedings ArticleDOI
Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing
D. Ingerly,S. Agraharam,D. Becher,V. Chikarmane,K. Fischer,R. Grover,M. Goodner,S. Haight,Jun He,T. Ibrahim,S. Joshi,H. Kothari,K. Lee,Y. Lin,C. Litteken,H. Liu,E. Mays,P. Moon,T. Mule,S. Nolen,N. Patel,S. Pradhan,J. Robinson,P. Ramanarayanan,S. Sattiraju,T. Schroeder,S. Williams,P. Yashar +27 more
TL;DR: In this article, the authors describe a 45nm high performance logic technology using carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film.
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