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J. Neirynck

Researcher at Intel

Publications -  7
Citations -  2465

J. Neirynck is an academic researcher from Intel. The author has contributed to research in topics: NMOS logic & PMOS logic. The author has an hindex of 7, co-authored 7 publications receiving 2335 citations.

Papers
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Proceedings ArticleDOI

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Kaizad Mistry, +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Proceedings ArticleDOI

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Proceedings ArticleDOI

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

P. Bai, +34 more
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Proceedings ArticleDOI

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

Sanjay Natarajan, +42 more
TL;DR: In this paper, a 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques.
Proceedings ArticleDOI

High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors

Paul A. Packan, +38 more
TL;DR: In this article, a 32nm logic technology for high performance microprocessors is described, and the impact of SRAM cell and array size on Vccmin is reported, including the effect of array size and cell cell cell size.