C. Pelto

TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.

TL;DR: In this paper, a 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques.

TL;DR: Ponte Vecchio (PVC) is a heterogenous petaop 3D processor comprising 47 functional tiles on five process nodes to operate as a single monolithic implementation enabling a scalable class of Exascale supercomputers.

TL;DR: In this paper , the authors discuss a new generation of heterogeneous integration architectures which they refer to as quasi-monolithic chips (QMC), which enable flexible out-of-order combinations of silicon process & packaging techniques to create flexible and ultra-high interconnect density 3D architectures to fit future computing & AI needs.

TL;DR: This paper presents the recent developments of on-chip low-loss passive circuits using customized patterns that are fabricated with standard bump process (C4) for RF, mmWave and sub-THz applications in Intel16 technology.