An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

http://science.sciencemag.org/content/sci/355/6322/271.full.pdf

Scaling carbon nanotube complementary transistors to 5-nm gate lengths

Radio-frequency identification (RFID) is a wireless data capturing technique that utilizes radio frequency (RF) waves for automatic identification of objects. RFID relies on RF waves for data transmission between the data carrying device, called the RFID tag, and the interrogator.

Chipless RFID: Bar Code of the Future

The accurate measurement of time lies at the heart of experimental science, and is relevant to everyday life. Extending chronoscopy to ever shorter timescales has been the key to gaining real-time insights into microscopic phenomena, ranging from vital biological processes to the dynamics underlying high technologies. The generation of isolated attosecond pulses in 2001 allowed the fastest of all motions outside the nucleus — electron dynamics in atomic systems — to be captured. Attosecond metrology has provided access to several hitherto immeasurably fast electron phenomena in atoms, molecules and solids. The fundamental importance of electron processes for the physical and life sciences, technology and medicine has rendered the young field of attosecond science one of the most dynamically expanding research fields of the new millennium. Here, we review the basic concepts underlying attosecond measurement and control techniques. Among their many potential applications, we focus on the exploration of the fundamental speed limit of electronic signal processing. This endeavour relies on ultimate-speed electron metrology, as provided by attosecond technology. This article reviews the basic concepts underlying attosecond measurement and control techniques. Emphasis is given to exploring the fundamental speed limit of electronic signal processing that employs ultimate-speed electron metrology provided by attosecond technology.

/pdf/attosecond-metrology-from-electron-capture-to-future-signal-2dadh1gxot.pdf

Attosecond metrology: from electron capture to future signal processing

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum2 cell size, containing >1.9 billion transistors.

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um I off . PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um I off . The impact of SRAM cell and array size on Vccmin is reported.

B. Song

Papers

A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors