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Min-Chie Jeng

Researcher at Cadence Design Systems

Publications -  5
Citations -  650

Min-Chie Jeng is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Gate oxide & MOSFET. The author has an hindex of 3, co-authored 5 publications receiving 631 citations.

Papers
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Journal ArticleDOI

Threshold voltage model for deep-submicrometer MOSFETs

TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
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A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

TL;DR: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation, which allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling.
Journal ArticleDOI

Temperature effects on MOSFET driving capability and voltage gain

TL;DR: In this article, the authors discuss the effect of temperature on MOSFET analogue applications and show that low temperature has greater benefit on current driving capability for analogue devices which have longer L and lower Vg values than digital ones.
Proceedings ArticleDOI

Deep-submicron MOSFET modeling for circuit simulation

TL;DR: In this paper, the authors describe recent activities and trends in MOSFET modeling and compare BSIM3 and MOS9, the two most discussed candidates for the standard deep-submicron MOS-FET model.
Journal ArticleDOI

Modeling of a MOSFET's parasitic resistance's narrow width and body bias effects for an IC simulator

TL;DR: Based on experimental data and physical understanding of the narrow width effect of source/drain parasitic series resistance of LDD MOSFETs, dimension and bias dependent models of Rds are derived and discussed in this article.