This dissertation focuses on efficiently forming reduced-order models for large, linear dynamic systems. Projections onto unions of Krylov subspaces lead to a class of reduced-order models known as rational interpolants. The cornerstone of this dissertation is a collection of theory relating Krylov projection to rational interpolation. Based on this theoretical framework, three algorithms for model reduction are proposed. The first
algorithm, dual rational Arnoldi, is a numerically reliable approach involving orthogonal projection matrices. The second, rational Lanczos, is an efficient generalization of existing Lanczos-based methods. The third, rational power Krylov, avoids orthogonalization and is suited for parallel or approximate computations. The performance of the three algorithms is compared via a combination of theory and examples. Independent of the precise algorithm, a host of supporting tools are also develop ed to form a complete model-reduction package. Techniques for choosing the matching frequencies, estimating the modeling error, insuring the model's stability, treating multiple-input multiple-output systems, implementing parallelism, and avoiding a need for exact factors of large matrix
pencils are all examined to various degrees

https://tel.archives-ouvertes.fr/tel-01711328/document

Krylov Projection Methods for Model Reduction

In this paper we present a new algorithm for accelerating the potential calculation which occurs in the inner loop of iterative algorithms for solving electromagnetic boundary integral equations. Such integral equations arise, for example, in the extraction of coupling capacitances in three-dimensional (3-D) geometries. We present extensive experimental comparisons with the capacitance extraction code FASTCAP and demonstrate that, for a wide variety of geometries commonly encountered in integrated circuit packaging, on-chip interconnect and micro-electro-mechanical systems, the new "precorrected-FFT" algorithm is superior to the fast multipole algorithm used in FASTCAP in terms of execution time and memory use. At engineering accuracies, in terms of a speed-memory product, the new algorithm can be superior to the fast multipole based schemes by more than an order of magnitude.

/pdf/a-precorrected-fft-method-for-electrostatic-analysis-of-4jonxbli4x.pdf

A precorrected-FFT method for electrostatic analysis of complicated 3-D structures

The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scali ng of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance—estimating both clock rate and IPC —of an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.

/pdf/clock-rate-versus-ipc-the-end-of-the-road-for-conventional-54d15znbzi.pdf

Clock rate versus IPC: the end of the road for conventional microarchitectures

Research in automatic analysis of sign language has largely focused on recognizing the lexical (or citation) form of sign gestures as they appear in continuous signing, and developing algorithms that scale well to large vocabularies. However, successful recognition of lexical signs is not sufficient for a full understanding of sign language communication. Nonmanual signals and grammatical processes which result in systematic variations in sign appearance are integral aspects of this communication but have received comparatively little attention in the literature. In this survey, we examine data acquisition, feature extraction and classification methods employed for the analysis of sign language gestures. These are discussed with respect to issues such as modeling transitions between signs in continuous signing, modeling inflectional processes, signer independence, and adaptation. We further examine works that attempt to analyze nonmanual signals and discuss issues related to integrating these with (hand) sign gestures. We also discuss the overall progress toward a true test of sign recognition systems?dealing with natural signing by native signers. We suggest some future directions for this research and also point to contributions it can make to other fields of research. Web-based supplemental materials (appendicies) which contain several illustrative examples and videos of signing can be found at www.computer.org/publications/dlib.

/pdf/automatic-sign-language-analysis-a-survey-and-the-future-3yh2fbjd5b.pdf

Automatic Sign Language Analysis: A Survey and the Future beyond Lexical Meaning

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

This paper presents an asynchronous SAR ADC for flexible, low energy radios. To achieve excellent power efficiency for a relatively moderate resolution, various techniques are introduced to reduce the power consumption: custom-designed 0.5 fF unit capacitors minimize the analog power consumption while asynchronous dynamic logic minimizes the digital power consumption. The variability of the custom-designed capacitors is estimated by a specialized CAD tool and verified by chip measurements. An implemented 8-bit prototype in a 90 nm CMOS technology occupies 228 μm × 240 μm including decoupling capacitors, and achieves an ENOB of 7.77 bit at a sampling frequency of 10.24 MS/s. The power consumption equals 26.3 μW from a 1 V supply, thus resulting in an energy efficiency of 12 fJ/conversion-step. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW. In that way, the energy efficiency of this converter can be maintained down to very low sampling rates.

A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios

https://repository.tudelft.nl/islandora/object/uuid%3A1dde3262-a4f7-4335-80a3-3c90a202e1fa/datastream/OBJ/download

VLSI circuit reconstruction from mask topology

An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. This paper proposes a Boundary Element Method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification.In contrast with standard BE methods, we propose a Green's function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor.

/pdf/extraction-of-circuit-models-for-substrate-cross-talk-4xvutc8mx6.pdf

Extraction of circuit models for substrate cross-talk

In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract circuits containing many thousands of substrate terminals. Examples are given that show that the method is sufficiently accurate for practical circuit verification. The method has been implemented in the layout-to-circuit extractor Space.

/pdf/fast-computation-of-substrate-resistances-in-large-circuits-2g6hfwp6nx.pdf

Fast computation of substrate resistances in large circuits

For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a Boundary Element Method (BEM) can be used. The FEM is the most versatile and flexible whereas the BEM is faster, but requires a stratified, layout-independent doping profile for the substrate. Thus, the BEM is unable to properly model any specific, layout-dependent doping patterns that are usually present in the top layers of the substrate, such as channel stop layers. This paper describes a way to incorporate these doping patterns into our substrate model by combining a BEM for the stratified doping profiles with a 2D FEM for the top-level, layout-dependent doping patterns, thereby achieving improved flexibility compared to BEM and improved speed compared to FEM. The method has been implemented in the SPACE layout to circuit extractor and it has been successfully verified with two other tools.

/pdf/combined-bem-fem-substrate-resistance-modeling-3hhg3cij1r.pdf

N.P. van der Meijs

Papers

A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios

VLSI circuit reconstruction from mask topology

Extraction of circuit models for substrate cross-talk

Fast computation of substrate resistances in large circuits

Combined BEM/FEM substrate resistance modeling