P
Peter A. Beerel
Researcher at University of Southern California
Publications - 236
Citations - 3784
Peter A. Beerel is an academic researcher from University of Southern California. The author has contributed to research in topics: Asynchronous communication & Computer science. The author has an hindex of 30, co-authored 208 publications receiving 3403 citations. Previous affiliations of Peter A. Beerel include Intel & University of California, San Diego.
Papers
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Patent
Optimization of cell subtypes in a hierarchical design flow
Frederik Eaton,Peter A. Beerel +1 more
TL;DR: In this article, a plurality cell instances are organized hierarchically, each cell instance corresponds schematically to one of a plurality of cell types, and each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell types by at least one transistor dimension.
Book
A Designer's Guide to Asynchronous VLSI
TL;DR: In this article, the authors present a practical guide to asynchronous design with a focus on practical techniques and real-world applications, as well as a large variety of design styles, while the emphasis throughout is on practical technique and real world applications.
Proceedings ArticleDOI
Speculative completion for the design of high-performance asynchronous dynamic adders
TL;DR: This paper presents an in-depth case study in high-performance asynchronous adder design that uses single-rail bundled datapaths but also allows early completion, and introduces five new dynamic designs for Brent-Kung and Carry-Bypass adders.
Proceedings ArticleDOI
Automatic gate-level synthesis of speed-independent circuits
Peter A. Beerel,Teresa H. Meng +1 more
TL;DR: This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efficient circuits compared to those synthesized with timing constraints.
Proceedings ArticleDOI
High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells
TL;DR: It is demonstrated that, by controlling top-block sizes and/or wire length within the place & route flow, ultra-high-performance circuits can be automatically designed.