R
R.D. Blanton
Researcher at Carnegie Mellon University
Publications - 158
Citations - 2948
R.D. Blanton is an academic researcher from Carnegie Mellon University. The author has contributed to research in topics: Automatic test pattern generation & Fault model. The author has an hindex of 31, co-authored 153 publications receiving 2707 citations. Previous affiliations of R.D. Blanton include University of Pittsburgh.
Papers
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Proceedings ArticleDOI
A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior
TL;DR: Results from several simulated and over 800 failing ICs reveal a significant improvement in localization and an accurate model of the logic-level defect behavior that provides useful insight into the actual defect mechanism.
Proceedings ArticleDOI
Properties of the input pattern fault model
R.D. Blanton,John P. Hayes +1 more
TL;DR: The IP fault model is described and a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools is provided, used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder.
Proceedings ArticleDOI
Development of a MEMS testing methodology
A. Kolpekwar,R.D. Blanton +1 more
TL;DR: This work describes the approach for developing a comprehensive testing methodology for a class of MEMS known as surface micromachined sensors and indicates that realistic contaminations can create a variety of defective structures that result in a wide spectrum of faulty behaviors.
Journal ArticleDOI
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits
TL;DR: This paper proposes a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially-correlated inter-die and/or intra-die variations in nanoscale manufacturing process, thereby reducing the cost of silicon characterization.
Proceedings ArticleDOI
Universal fault simulation using fault tuples
K.N. Dwarakanath,R.D. Blanton +1 more
TL;DR: A new fault representation mechanism for digital circuits based on fault tuples, which shows a 17% reduction of average CPU time when performing sim ulation on all fault types simultaneously, as opposed to individually.