There is great interest in developing rechargeable lithium batteries with higher energy capacity and longer cycle life for applications in portable electronic devices, electric vehicles and implantable medical devices. Silicon is an attractive anode material for lithium batteries because it has a low discharge potential and the highest known theoretical charge capacity (4,200 mAh g(-1); ref. 2). Although this is more than ten times higher than existing graphite anodes and much larger than various nitride and oxide materials, silicon anodes have limited applications because silicon's volume changes by 400% upon insertion and extraction of lithium which results in pulverization and capacity fading. Here, we show that silicon nanowire battery electrodes circumvent these issues as they can accommodate large strain without pulverization, provide good electronic contact and conduction, and display short lithium insertion distances. We achieved the theoretical charge capacity for silicon anodes and maintained a discharge capacity close to 75% of this maximum, with little fading during cycling.

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High-performance lithium battery anodes using silicon nanowires

Since the discovery of mechanically exfoliated graphene in 2004, research on ultrathin two-dimensional (2D) nanomaterials has grown exponentially in the fields of condensed matter physics, material science, chemistry, and nanotechnology. Highlighting their compelling physical, chemical, electronic, and optical properties, as well as their various potential applications, in this Review, we summarize the state-of-art progress on the ultrathin 2D nanomaterials with a particular emphasis on their recent advances. First, we introduce the unique advances on ultrathin 2D nanomaterials, followed by the description of their composition and crystal structures. The assortments of their synthetic methods are then summarized, including insights on their advantages and limitations, alongside some recommendations on suitable characterization techniques. We also discuss in detail the utilization of these ultrathin 2D nanomaterials for wide ranges of potential applications among the electronics/optoelectronics, electrocat...

Recent Advances in Ultrathin Two-Dimensional Nanomaterials

In this chapter, we will restrict our attention to the ferrites and a few other closely related materials. The great interest in ferrites stems from their unique combination of a spontaneous magnetization and a high electrical resistivity. The observed magnetization results from the difference in the magnetizations of two non-equivalent sub-lattices of the magnetic ions in the crystal structure. Materials of this type should strictly be designated as “ferrimagnetic” and in some respects are more closely related to anti-ferromagnetic substances than they are to ferromagnetics in which the magnetization results from the parallel alignment of all the magnetic moments present. We shall not adhere to this special nomenclature except to emphasize effects, which are due to the existence of the sub-lattices.

Ferromagnetic materials

This article presents an overview of the essential aspects in the fabrication of silicon and some silicon/germanium nanostructures by metal-assisted chemical etching. First, the basic process and mechanism of metal-assisted chemical etching is introduced. Then, the various influences of the noble metal, the etchant, temperature, illumination, and intrinsic properties of the silicon substrate (e.g., orientation, doping type, doping level) are presented. The anisotropic and the isotropic etching behaviors of silicon under various conditions are presented. Template-based metal-assisted chemical etching methods are introduced, including templates based on nanosphere lithography, anodic aluminum oxide masks, interference lithography, and block-copolymer masks. The metal-assisted chemical etching of other semiconductors is also introduced. A brief introduction to the application of Si nanostructures obtained by metal-assisted chemical etching is given, demonstrating the promising potential applications of metal-assisted chemical etching. Finally, some open questions in the understanding of metal-assisted chemical etching are compiled.

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Metal-Assisted Chemical Etching of Silicon: A Review

In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Phase Change Memory

This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.

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Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties

Silicon nanowires have been identified as important components for future electronic and sensor nanodevices. So far gold has dominated as the catalyst for growing Si nanowires via the vapour-liquid-solid (VLS) mechanism. Unfortunately, gold traps electrons and holes in Si and poses a serious contamination problem for Si complementary metal oxide semiconductor (CMOS) processing. Although there are some reports on the use of non-gold catalysts for Si nanowire growth, either the growth requires high temperatures and/or the catalysts are not compatible with CMOS requirements. From a technological standpoint, a much more attractive catalyst material would be aluminium, as it is a standard metal in Si process lines. Here we report for the first time the epitaxial growth of Al-catalysed Si nanowires and suggest that growth proceeds via a vapour-solid-solid (VSS) rather than a VLS mechanism. It is also found that the tapering of the nanowires can be strongly reduced by lowering the growth temperature.

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Epitaxial growth of silicon nanowires using an aluminium catalyst

We found that silicon nanowires grown epitaxially on Si (100) via the vapor−liquid−solid growth mechanism change their growth direction from 〈111〉 to 〈110〉 at a crossover diameter of approximately 20 nm. A model is proposed for the explanation of this phenomenon. We suggest that the interplay of the liquid−solid interfacial energy with the silicon surface energy expressed in terms of an edge tension is responsible for the change of the growth direction. The value of the edge tension is estimated by the product of the interfacial thickness with the surface energy of silicon. For large diameters, the direction with the lowest interfacial energy is dominant, whereas for small diameters the surface energy of the silicon nanowire determines the preferential growth direction.

Diameter-dependent growth direction of epitaxial silicon nanowires.

Semiconducting nanowires have recently attracted considerable attention. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well as for technology. A variety of technical applications, such as nanowires as parts of sensors, and electronic and photonic devices have already been demonstrated. In particular, electronic applications come more and more into focus, as the ongoing miniaturization in microelectronics demands new innovative solutions. Semiconducting nanowires, in particular epitaxially grown silicon (Si) nanowires, are considered as promising candidates for post-CMOS (CMOS: complementary metal–oxide semiconductor) logic elements owing to their potential compatibility with existing CMOS technology. One major advantage of vapor–liquid– solid(VLS-) grown nanowires compared to top-down fabricated devices is that they have well-defined surfaces. This reduces surface scattering, an issue which becomes important for devices on the nanoscale. Moreover, epitaxially grown nanowires circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-and-place approach, where devices are fabricated by manipulating horizontally lying VLS-grown nanowires. The first step towards a technical realization of a nanowire logic element is the design and manufacturing of a nanowire transistor. The epitaxial growth of vertical nanowires offers advantages over other approaches: For example, the transistor gate can be wrapped around the vertically oriented nanowire. Such a wrapped-around gate allows better electrostatic gate control of the conducting channel and offers the potential to drive more current per device area than is possible in a conventional planar architecture. In this Communication, a generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described. Exemplarily, we used Si nanowires and present a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device. Figure 1a shows a schematic cross section through a conventional p-type MOSFET. In such a device, an inversion channel can be created close to the gate by applying a negative gate voltage. This forms a conducting channel that connects the p-doped regions between the source and drain contacts electrically. Using this concept, a silicon nanowire VS-FET would ideally require a nanowire that is n-doped in the region of the gate and p-doped elsewhere. Unfortunately, such a p-n-p structure with abrupt transitions appears difficult to realize if the nanowires are grown by means of the vapor–liquid–solid mechanism using gold as a catalyst. The difficulty here is that the dopant atoms, which are dissolved in the catalyst droplet, might act as a reservoir, thus creating a graded transition when switching to another dopant. Therefore, we used a structure consisting of an n-doped silicon nanowire grown on a p-type substrate (see Figure 1b). If the gate–drain and gate–source distances are not too long, it is electrostatically still possible to create an inversion channel along the length of the entire wire. In the proposed configuration, the p–n junction at the source contact (Figure 1a) is replaced by a Au/n-Si Schottky contact at the nanowire tip. In order to investigate the influence of the Au/n-Si Schottky contact on the nanowire (current–voltage) I–V characteristics, an array of n-doped nanowires vertically grown on an n-type (111)-oriented substrate was imbedded in a spin-coated SiO2 matrix. After removing the thin SiO2 coverage from the Au tips by a short reactive ion etching, contacts 0.6 mm in size were defined by evaporating aluminum onto the sample, such that approximately 10 nanowires were contacted in parallel. The temperature-dependent measurements (shown in Figure 2) were performed by applying a voltage to the Si substrate, while the Al top contact was held at a constant potential. The measurements reveal a strong rectifying behavior with a thermally activated current possessing an activation energy of 0.6 eV. This can be explained by the Au/n-Si Schottky contact dominating the I–V behavior. The fact that the Schottky contact is forward-biased for negative voltages furthermore proves that, as expected, electrons act as majority charge carries. Figure 1. Schematics of a) a conventional p-channel MOSFET and b) a silicon nanowire vertical surround-gate field-effect transistor.

Realization of a silicon nanowire vertical surround-gate field-effect transistor.

Ferroelectric materials have emerged in recent years as an alternative to magnetic and dielectric materials for nonvolatile data-storage applications1,2,3,4,5. Lithography is widely used to reduce the size of data-storage elements in ultrahigh-density memory devices6,7,8,9. However, ferroelectric materials tend to be oxides with complex structures that are easily damaged by existing lithographic techniques, so an alternative approach is needed to fabricate ultrahigh-density ferroelectric memories. Here we report a high-temperature deposition process that can fabricate arrays of individually addressable metal/ferroelectric/metal nanocapacitors with a density of 176 Gb inch−2. The use of an ultrathin anodic alumina membrane as a lift-off mask makes it possible to deposit the memory elements at temperatures as high as 650 °C, which results in excellent ferroelectric properties. Ferroelectric oxides have emerged as candidate materials for non-volatile data-storage applications, but they can be difficult to process. Researchers have now used a high-temperature deposition process to fabricate arrays of metal–ferroelectric–metal nanocapacitors with a density of 176 gigabits per square inch.

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Stephan Senz

Papers

Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties

Epitaxial growth of silicon nanowires using an aluminium catalyst

Diameter-dependent growth direction of epitaxial silicon nanowires.

Realization of a silicon nanowire vertical surround-gate field-effect transistor.

Individually addressable epitaxial ferroelectric nanocapacitor arrays with near Tb inch −2 density