Tatsuya Ohguro

TL;DR: In this article, the authors explained the NiSi salicide technology and showed that NiSi has several advantages over TiSi2 and CoSi2 for the ultra-small CMOS process, including low temperature silicidation process, low silicon consumption, no bridging failure property, smaller mechanical stress, no adverse narrow line effect on sheet resistance, smaller contact resistance for both n- and p-Si, and higher activation rate of B for SiGe poly gate electrode.

TL;DR: In this paper, a 1.5 nm direct-tunneling gate oxide was used to achieve a transconductance of more than 1,000 mS/mm at a gate length of 0.09 /spl mu/m at room temperature.

TL;DR: In this article, a nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed, and it has been confirmed that a nickel film sputtered onto n/sup ± and p/sup +/- single-silicon and polysilicon substrates is uniformly converted into NiSi, without agglomeration, by lowtemperature (400-600/spl deg/C) rapid thermal annealing.

TL;DR: In this paper, the relationship between sheet resistance and line width is characterized by three distinct regions according to the value of W. The abrupt increase in sheet resistance observed in the region W/spl les/0.2 /spl mu/m cannot be explained in terms of the phase transition from C54 to C49, which is the cause of the rising resistance at larger W.

TL;DR: In this paper, a 40-nanometer gate length n-MOSFET with ultra-shallow source and drain junctions of around 10 nm was fabricated for the first time using a technique of solid phase diffusion (SPD) from phosphorous-doped silicated glass gate sidewalls.