Showing papers by "Tetsu Tanaka published in 2016"

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration.

Abstract: Plasma- and water-assisted oxide-oxide thermocompression direct bonding for a self-assembly based multichip-to-wafer (MCtW) 3D integration approach was demonstrated. The bonding yields and bonding strengths of the self-assembled chips obtained by the MCtW direct bonding technology were evaluated. In this study, chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PE-CVD) as a MCtW bonding interface was mainly employed, and in addition, wafer-to-wafer thermocompression direct bonding was also used for comparison. N2 or Ar plasmas were utilized for the surface activation. After plasma activation and the subsequent supplying of water as a self-assembly mediate, the chips with the PE-CVD oxide layer were driven by the liquid surface tension and precisely aligned on the host wafers, and subsequently, they were tightly bonded to the wafers through the MCtW oxide-oxide direct bonding technology. Finally, a mechanism of oxide-oxide direct bonding to support the previous models was discussed using an atmospheric pressure ionization mass spectrometer (APIMS).

Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC

Abstract: A three-dimensional stacked IC (3D IC) is a one of the promising structures for enhancing IC performances. A 3D IC consists of several materials such as a Si substrate, metal for through Si via (TSV) and microbump, organic adhesive called the underfill, and so on. These materials generate a coefficient of thermal expansion (CTE) mismatch. On the other hand, heat is generated in the Si substrate during circuit operation and in the environment outside 3D IC, for example. Both the CTE mismatch and heat generation induce local stress caused by expansion of the underfill injected around metal microbumps. In this paper, we report our investigation results of the effects of adhesive expansion on transistor performances by finite element method (FEM) simulation and measurement of transistor characteristics.

Capillary Self-Assembly for 3D Heterogeneous System Integration and Packaging

Abstract: The self-assembly of known good dies (KGDs) on substrates using the liquid capillary method is shown to be a promising technology to achieve three-dimensional (3D) heterogeneous system integration and packaging. Firstly, the effects of the edge structures of self-assembled substrates and chips on alignment accuracies were investigated. When hydrophobic sidewalls with 10-µm-height steps were applied to both chips and assembly sites formed on substrates, the alignment accuracy within 1.0 µm was realized. The alignment accuracies were within 2.0 µm using either substrates or chips having 10-µm-height step structures with hydrophobic sidewalls. Self-assembly of 12-ch vertical-cavity surface-emitting lasers (VCSELs) with a long rectangle shape on glass substrates were also demonstrated. Separation of assembly sites into twelve areas enhanced the resultant force acting on the VCSEL short edge. The enhanced resultant force provided the high alignment accuracies within 2.0 μm. After the self-assembly of the VCSEL and the subsequent thermal compression, the chips successfully exhibited no degradation of their current–voltage (I–V) characteristics and appropriate 850-nm light emission. We demonstrated self-assembly and microbump bonding using non-conductive film (NCF)-covered dies with Cu/Sn microbumps for high-throughput and high-yield multichip-to-wafer 3D integration. The self-assembly of the NCF-covered dies provided high alignment accuracy within 1.1 μm on average. After the self-assembly of NCF-coved dies and thermal compression, microbump chains composed of 7396 bump joints were successfully obtained, resulting in good electrical properties of 32 mΩ/joint without any bridge shorts and failures. The variations of microbump joint resistance were maintained within 5% of the initial value after thermal cycle testing of even 1000 cycles.

Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration

Abstract: The self-assembly of known good dies on hosting substrates using liquid surface tension is a promising technology to create highly integrated 3-D and heterogeneous microelectronic systems. In this paper, we investigate the effects of the edge structures of self-assembled chips on alignment accuracies. Nine types of 100- $\mu \text{m}$ -thick Si chips (3 mm $\times \,\, 3$ mm) with and without step geometries on their hydrophilic or hydrophobic peripheries are self-assembled onto hydrophilic assembly sites formed on planar- and plateau-type host substrates. When hydrophobic peripheries with step geometries are applied to both the edges of chips and assembly sites formed on substrates, the resulting average alignment accuracy is 300 nm. Total accuracy variation within 2 $\mu \text{m}$ is realized by using either chip or substrate having 10- $\mu \text{m}$ -height step structures with hydrophobic edges. We obtain a high tolerance for initial offsets indicating positioning misalignment prior to chip release, with the plateau-type substrates and the chips having hydrophobic step structures at the edges. These chips are precisely self-assembled, even under a large initial offset of 1.5 mm in a horizontal direction to both the substrates. The extremely large offset is comparable with 50% of the side length of the 3-mm-square chip. On the other hand, the chips formed by an accurate saw dicing that gives high chip-size accuracies as designed exhibit high alignment accuracies and tolerances when compared with the chips with the hydrophobic step structures and the chips formed by plasma dicing, which offer a large pseudo step with a height of $100~\mu \text{m}$ . [2014-0298]

Novel W2W/C2W Hybrid Bonding Technology with High Stacking Yield Using Ultra-Fine Size, Ultra-High Density Cu Nano-Pillar (CNP) for Exascale 2.5D/3D Integration

Abstract: We propose a novel hybrid bonding technology with a high stacking yield using ultra-high density Cu nano-pillar (CNP) for exascale 2.5D/3D integration. To solve the critical issues of current standard hybrid bonding technology, we developed scaled electrodes with slightly extruded structure and unique adhesive layer of anisotropic conductive film composed of untra-fine size, ultra-high density CNP. Multi-number of TEG dies with 7mm x 23mm size are bonded to an interposer wafer by a new hybrid bonding technology. A huge number of electrodes of 4,309,200 composed of scaled electrodes with 3µm diameter and 6µm pitch are formed in each TEG die. We confirmed for the first time that 4,309,200 electrodes per die are successfully connected in series with the joining yield of 100% due to ultra-high density CNP.

Novel Hybrid Bonding Technology Using Ultra-High Density Cu Nano-Pillar for Exascale 2.5D/3D Integration

Abstract: We propose a novel hybrid bonding technology with a high stacking yield using ultra-high density Cu nano-pillar (CNP) for exascale 2.5D/3D integration. To solve the critical issues of a current standard hybrid bonding technology, we developed scaled electrodes with slightly extruded structure and unique adhesive layer of anisotropic conductive film composed of ultra-high density CNP. Test element group (TEG) dies with 7-mm $\times 23$ -mm size are bonded to interposer wafer by a new hybrid bonding technology. Scaled electrodes with 3- $\mu \text{m}$ diameter and 6- $\mu \text{m}$ pitch are formed in each TEG chip. We confirmed for the first time that a huge number of electrodes of 4 309 200 are successfully connected in series with the joining yield of 100% due to the ultra-high density CNP.

Design and evaluation of area-efficient and wide-range impedance analysis circuit for multichannel high-quality brain signal recording system

Abstract: To enable chronic and stable neural recording, we have been developing an implantable multichannel neural recording system with impedance analysis functions. One of the important things for high-quality neural signal recording is to maintain well interfaces between recording electrodes and tissues. We have proposed an impedance analysis circuit with a very small circuit area, which is implemented in a multichannel neural recording and stimulating system. In this paper, we focused on the design of an impedance analysis circuit configuration and the evaluation of a minimal voltage measurement unit. The proposed circuit has a very small circuit area of 0.23 mm2 designed with 0.18 µm CMOS technology and can measure interface impedances between recording electrodes and tissues in ultrawide ranges from 100 Ω to 10 MΩ. In addition, we also successfully acquired interface impedances using the proposed circuit in agarose gel experiments.

Transfer and Non-transfer 3D Stacking Technologies Based on Multichip-to-Wafer Self-Assembly and Direct Bonding

Abstract: Non-transfer and transfer based 3D integration technologies are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Both the stacking approaches employ KGD self-assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-treated plasma-TEOS SiO2 on their top surface are directly self-assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.

Heterogeneous 3-D Integration Using Self-Assembly and Electrostatic Bonding

Abstract: To overcome various concerns caused by scaling down the device size in future Large Scale Integrated Circuits (LSIs), it is indispensable to introduce a new concept of heterogeneous 3-D integration in which various kinds of device chips with different sizes, different devices, and different materials are vertically stacked. To achieve such heterogeneous 3-D integration, a key technology of self-assembly and electrostatic bonding has been developed. Exploring new devices for the Internet of Things, we have fabricated several kinds of heterogeneous 3-D LSIs called superchip by stacking compound semiconductor device chip, photonic device chip, and spintronic device chip on CMOS device chips using self-assembly and electrostatic bonding. Furthermore, a new system integration technology using a large-area substrate has been developed to reduce the cost of 2.5-D/3-D system module. A 3-D-stacked image sensor system module for automatic driving vehicle has been fabricated using this technology.

New multichip-to-wafer 3D integration technology using Self-Assembly and Cu nano-pillar hybrid bonding

Abstract: New 3D integration technology using self-assembly and Cu nano-pillar hybrid bonding are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled with a high alignment accuracy making use of liquid surface tension in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier and electrostatically bonded by applying a voltage to bipolar electrodes on the SAE carrier. The self-assembled dies on the carrier are simultaneously transferred to another wafer or interposer wafer by electrostatically debonding the carrier wafer after Cu nano-pillar hybrid bonding of self-assembled dies.

Back-via 3D integration technologies by temporary bonding with thermoplastic adhesives and visible-laser debonding

Abstract: Back-via three-dimensional (3D) integration using multiple thin-wafer transfer processes has been developed at GINTI, Tohoku University, where visible laser was employed for wafer debonding. The potential advantages of laser debonding are (i) the realization of ultra-thin wafer releasing with less stress as compared to the conventional thermal and chemical debonding methods, and (ii) no adhesive residues were left on the thinned wafer surface owing to their excellent solubility in solvents. The edge-trimming width and depth for Si before temporary bonding and the temporary bonding parameters using thermo-plastic adhesives were carefully investigated and optimized, in order to avoid any undesirable effects in background thin wafers. Through-Si-Vias with a diameter of 5–15 µm were formed by masking the via patterns (using i-line, back-side-alignment) on the SiO2 surface of the back-ground side of 30 – 50 µm-thick LSI wafer that was temporarily bonded to the support glass, followed by selective deep-reactive-ion-etching of SiO2, Si, and bottom SiO2, and subsequently barrier and seed layers deposition and via filling. Using laser debonding technique, the thinned Si wafers with Cu-vias were transferred to the other glass with different temporary adhesive. The observed low resistance values from the I–V data for 5000 Cu-via daisy chain reveals that the proposed back-via 3D integration using laser debonding is now ready for industrial use.

New concept of TSV formation methodology using Directed Self-Assembly (DSA)

Abstract: A new TSV formation methodology based on advanced Directed Self-Assembly (DSA) with nanocomposites consisting of nano metal particles and block-co-polymers is proposed in this paper. Cylindrical nano-ordered structures are formed in Si deep holes through phase separation of polystyrene-block-poly methyl methacrylate polymers (PS-b-PMMA). The impact of molecular weight of the polymers, composition (PS/PMMA ratio), and phase separation temperature on the morphologies is discussed. In addition, simulation results using Self-Consistent Field (SCF) theory are introduced to make fine-pitch TSV.

Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler

Abstract: Three-dimensional IC (3D IC) is a promising method to enhance IC performance. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we propose a novel underfill with negative-CTE filler which can suppress the local bending stress in 3D IC.

Non-conductive film underfill for 3D integration of 20 pm-thick LSI wafers with fine Cu-TSVs

Abstract: The beneficial role played by non-conductive film (NCF) under-fill (UF) compared with the conventional capillary under fill (CUF) is meticulously investigated for the reliability issues in high-density 3D-integration at die/wafer-level. The NCF with co-efficient of thermal expansion (CTE) value of 35 ppm/°C tremendously reduces the local deformation of 20 pm-thick three-dimensionally (3D)-stacked LSI die/wafer. This reduces the local mechanical stress in thinned 3D-LSI by nearly 5 times as against the CUF with the CTE value of 60–70 ppm/C. Both μ-RS and μ-XRD data showed only ∼250 MPa of tensile stress on the back surface of 20 pm-thick stacked die/wafer with NCFUF, whereas it was more than five-times larger (∼1400 MPa) for CUF. μ-XRD data illustrates that the cause for residual stress in the bump-space region and above the μ-bump are respectively due to the lattice tilt and change in lattice space.

Wide-range and precise tissue impedance analysis circuit with ultralow current source using gate-induced drain-leakage current

Abstract: This paper presents a bioelectrical impedance analysis circuit with ultralow-current source using gate-induced drain-leakage (GIDL) current for biomedical applications. The proposed circuit consists of an ultralow-current reference circuit, a minimal voltage measurement block, a precise current source block, and a digital control logic circuit. The reference circuit generates pico-ampere-order currents based on GIDL current of an n-channel MOSFET. Fabricated in a 0.18μm 1P6M standard CMOS technology, the impedance analysis circuit occupies 0.27mm2 and can measure impedance range from 100Ω to 10MΩ. Experimental results shows that the fabricated current source using GIDL current generates a quite stable ultralow-current of 50pA, 100pA and 200pA, respectively. In addition, the proposed analysis circuit successfully measures the electrode-tissue interface impedance and tissue impedance by functional verification using monolayer and inhomogeneous agarose gel test setup phantom.

Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

Abstract: As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips.

Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip

Abstract: The effect of local stresses on memory retention characteristics has been characterized in detail. A retention time of memory cells in a DRAM chip with 200-μm thick was largely changed after under-fill shrinkage with Cu/Sn bumps. Meanwhile, after thinned down to 40-μm thick, the retention time of memory cell was not significantly changed in the whole area even with Cu/Sn bumps due to decreased stress. We showed that the local stress generated by under-fill shrinkage with the dummy Cu/Sn bumps gave larger effects on the memory retention characteristics than the stress generated by the Si thinning until 40-μm thick.

Highly sensitive pressure sensor with silicon-on-nothing (SON) MOSFET for sensor integrated heterogeneous system

Abstract: MOSFETs have the potential to be-come a highly sensitive pressure sensor compared with conventional piezoresistive device such as doped Si. In this study, we have proposed a novel pressure sensor composed of silicon-on-nothing (SON) MOSET. It was clearly indicated that the SON-MOSFET had high gauge factor of 230 which was more than twice as high as conventional values. These results expedite developments and realization of sensor integrated heterogeneous system.

Impact of Interconnections on Vertically Stacked 20 um-Thick DRAM Chips

Abstract: Effect of thermo-mechanical stress (TMS) originating from CuSn micro-bumps (µ-bumps) and Cu through-Si-vias (TSVs) on the retention characteristics of 20-µm-thick, vertically stacked dynamic random access memory (DRAM) chip has been investigated. At cumulative probability of 50 %, the retention period decreased nearly 47% for the DRAM chip having thickness value of 20 µm as compared to the retention period of 200 µm-thick DRAM chip. Annealing at 300 °C, a compressive stress value of -200 MPa caused by Cu-TSVs was observed as the remnant stress at the periphery of the keep-out-zone, and faded quickly by moving away from the keep -- out-zone. We did observe tle dependency of DRAM retention time on the TMS caused by TSVs. In the case of µ-bump, we observed a large amount of tensile stress (> +300 MPa) on the back-side of DRAM chip at right above the CuSn µ-bumps, and it led to a crack in the DRAM chip. As compared to CuSn µ-bumps, the polyimide dummy µ-bumps present in between two chip layers induced less amount of residual stress in the DRAM chip.

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSi x for via-last TSV technology

Abstract: With in the process temperature limit of less than 400 °C for via last technology, a simple method to improve the barrier ability of Ti layer in through Si via (TSV) has been studied. After annealing the TSV structures in vacuum at temperatures up to 400 °C, we did observe a tremendous improvement in leak current characteristics for SiO2 dielectric. It was found that the self-formed TiSi x at the interface between Cu and SiO 2 during the sputter deposition of Ti barrier layer was converted into an amorphous TiOx and SiOx upon vacuum annealing. This simple vacuum annealing of Cu-TSVs is a promising approach for using Ti as barrier layer in via-last 3D-integration.