T
Thomas Hoffmann
Researcher at Intel
Publications - 16
Citations - 680
Thomas Hoffmann is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 11, co-authored 15 publications receiving 675 citations.
Papers
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Proceedings ArticleDOI
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell
Scott E. Thompson,Nidhi Anand,Mark Armstrong,C. Auth,B. Arcot,Mohsen Alavi,P. Bai,J. Bielefeld,Robert M. Bigwood,J. Brandenburg,M. Buehler,Stephen M. Cea,V. Chikarmane,C. H. Choi,R. Frankovic,Tahir Ghani,G. Glass,W. Han,Thomas Hoffmann,Makarem A. Hussein,P. Jacob,Ajay Jain,Chia-Hong Jan,Subhash M. Joshi,C. Kenyon,Jason Klaus,S. Klopcic,J. Luce,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,P. Nguyen,H. Pearson,T. Sandford,R. Schweinfurth,R. Shaheed,Swaminathan Sivakumar,M. Taylor,B. Tufts,Charles H. Wallace,P.-H. Wang,Cory E. Weber,Mark T. Bohr +43 more
TL;DR: In this paper, a leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented.
Patent
Method for improving transistor performance through reducing the salicide interface resistance
TL;DR: In this article, a silicon germanium alloy was used to form the contact surface of the source and drain regions of a transistor, which reduced the external resistance of the transistor by using a nickel silicon-germanium self-aligned silicide layer.
Patent
Gate-induced strain for MOS performance improvement
TL;DR: In this paper, an apparatus including a substrate defining an interior of the apparatus, a device exterior to the substrate including a gate electrode, and a straining layer exterior to both the gate electrode and the substrate is disclosed.
Patent
Increasing stress-enhanced drive current in a MOS transistor
TL;DR: In this article, an intentional recess or indentation is created in a region of semiconductor material that will become part of a channel of a metal oxide semiconductor (MOS) transistor structure.
Proceedings ArticleDOI
Understanding stress enhanced performance in Intel 90nm CMOS technology
Martin D. Giles,Mark Armstrong,C. Auth,S. Cea,Tahir Ghani,Thomas Hoffmann,Roza Kotlyar,Philippe Matagne,Kaizad Mistry,Ramune Nagisetty,B. Obradovic,R. Shaheed,Lucian Shifren,M. Stettler,S. Tyagi,Xiaofei Wang,Cory E. Weber,K. Zawadzki +17 more
TL;DR: A hierarchical, model-based understanding of the key physical effects underlying stress-induced device performance gain is presented in this paper, focusing on the large gains seen for uniaxial PMOS stress conditions and the vertical stress impact on NMOS gain.